IC61LV256-10JG ICSI [Integrated Circuit Solution Inc], IC61LV256-10JG Datasheet
IC61LV256-10JG
Related parts for IC61LV256-10JG
IC61LV256-10JG Summary of contents
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... IC61LV256 Document Title 32K x 8 Hight Speed SRAM with 3.3V Revision History Revision No History 0A Initial Draft 0B Add Pb-free parts The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. ...
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... CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) con- trols both writing and reading of the memory. The IC61LV256 is available in the JEDEC standard 28-pin, 300mil SOJ and the 8*13.4mm TSOP-1 package. DECODER MEMORY ARRAY ...
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... IC61LV256 PIN CONFIGURATION 28-Pin SOJ A14 1 28 VCC A12 A13 A11 A10 I/O7 I/ I/O6 I/ I/O5 I/ I/O4 GND 14 15 I/O3 PIN DESCRIPTIONS A0-A14 Address Inputs CE Chip Enable Input OE Output Enable Input ...
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... IC61LV256 OPERATING RANGE Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage ( Input Leakage LI I Output Leakage LO Notes (min.) = – ...
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... IC61LV256 READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time RC t Address Access Time AA t Output Hold Time OHA t CE Access Time ACE t OE Access Time DOE Low-Z Output (2) LZOE High-Z Output (2) HZOE Low-Z Output (2) LZCE t ( High-Z Output ...
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... IC61LV256 AC WAVEFORMS READ CYCLE NO. 1 (1,2) ADDRESS D OUT PREVIOUS DATA VALID READ CYCLE NO. 2 (1,3) ADDRESS LZCE HIGH-Z D OUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE Address is valid prior to or coincident with CE LOW transitions OHA ...
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... IC61LV256 WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time Write End SCE t Address Setup Time AW to Write End t Address Hold HA from Write End t Address Setup Time Pulse Width (4) PWE t Data Setup to Write End SD t Data Hold from Write End ...
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... IC61LV256 WRITE CYCLE NO. 2 (WE Controlled HIGH During Write Cycle) ADDRESS OE CE LOW DATA UNDEFINED OUT D IN WRITE CYCLE NO. 3 (WE Controlled LOW During Write Cycle) ADDRESS LOW OE CE LOW DATA UNDEFINED OUT D IN Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write ...
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... IC61LV256-15T IC61LV256-15J ORDERING INFORMATION (Pb-free) Commercial Range: 0°C to +70°C Speed (ns) Order Part No. 8 IC61LV256-8TG IC61LV256-8JG 10 IC61LV256-10TG IC61LV256-10JG 12 IC61LV256-12TG IC61LV256-12JG 15 IC61LV256-15TG IC61LV256-15JG NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, Integrated Circuit Solution Inc. 11/28/2003 AHSR027-0B ORDERING INFORMATION Industrial Range: –40°C to +85°C ...