PE3291EK PEREGRINE [Peregrine Semiconductor Corp.], PE3291EK Datasheet - Page 7

• Manufacturer Part Number: PE3291EK
• Manufacturer: PEREGRINE [Peregrine Semiconductor Corp.]

PE3291
Product Specification
Functional Description
The Functional Block Diagram in Figure 7 shows a
21-bit serial control register, a multiplexed output,
and PLL sections PLL1 and PLL2. Each PLL
contains a fractional-N main counter chain, a
reference counter, a phase detector, and an
internal charge pump with on-chip fractional spur
compensation. Each fractional-N main counter
chain includes an internal dual modulus prescaler,
supporting counters, and a fractional accumulator.
Serial input data is clocked on the rising edge of
Clock, MSB first. The last two bits are the address
bits that determine the register address. Data is
transferred into the counters as shown in Table 8,
PE3291 Register Set. If the f
as data out, then the contents of shift register bit
S
the f
compatible devices to be connected in a daisy-
chain configuration.
The PLL1 (RF) VCO frequency f
Figure 7. Functional Block Diagram
Document No. 70-0009-04 │ www.psemi.com
20
are clocked on the falling edge of Clock onto
o
LD pin. This feature allows the PE3291 and
Clock
Data
f
f
LE
in
in
1
2
f
r
Amp.
Ref.
o
Prescaler
Prescaler
LD pin is configured
P
32/33
16/17
P
1
1
in
P
P
1 is related to
2
2
21-bit Serial Control
Interface
9-bit Reference
9-bit Reference
M
M
A
A
3<M
3<M
Divider
Divider
0<A
0<A
1
2
1
2
Counter
Counter
Counter
Counter
R
R
9
9
M
M
A
1
2
1
2
4
A
9
9
1
2
5
<511
<511
2
1
2
1
<31
<15
Control Logic
Control Logic
F
F
Prescaler
0<F
0<F
Prescaler
1
2
Counter
Counter
F
F
5
1
2
5
2
1
<31
<31
the reference frequency f
equation:
f
(1) Note that A
must be greater than or equal to 1024 x (f
obtain contiguous channels.
The PLL2 (IF) VCO frequency f
reference frequency f
f
(2) Note that A
must be greater than or equal to 256 x (f
obtain contiguous channels.
F
the PE3291 automatically reduces the fraction.
For example, if F
automatically reduced to 3/8. In this way,
fractional denominators of 2, 4, 8, 16 and 32 are
available. F
same manner.
in
in
Detector
1
Detector
Phase
1 = [(32 x M
2 = [(16 x M2) + A
Phase
sets PLL1 fractionality. If F
C
C
Multiplexer
11
21
©2005 Peregrine Semiconductor Corp. All rights reserved.
Fractional Spur
Fractional Spur
Compensation
Compensation
2
C
C
Charge
Charge
sets the fractionality for PLL2 in the
12
22
Pump
Pump
1
1
2
) + A
must be less than M
must be less than M
1
= 12, then the fraction 12/32 is
1
2
C
C
C
C
+ (F
r
22
22
22
22
+ (F
by the following equation:
r
1
2
/32)] x (f
by the following
f
/32)] x (f
CP1
CP2
o
LD
1
is an even number,
in
2 is related to the
r
/R
r
/R
1
2
. Also, f
. Also, f
1
2
)
)
r
Page 7 of 15
/R
r
/R
2
) to
1
in
in
) to
1
2