AZ100LVEL16VV_12 AZM [Arizona Microtek, Inc], AZ100LVEL16VV_12 Datasheet - Page 3

• Manufacturer Part Number: AZ100LVEL16VV_12
• Description: Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable
• Manufacturer: AZM [Arizona Microtek, Inc]

Arizona Microtek, Inc.
E
The data inputs are selected with the select pin (SEL). When SEL is LOW or open (NC) data from the D0/D0
When SEL is HIGH data from the D1/D1
The enable pin (EN) works with either data input pair. When EN is HIGH or open (NC), input data is passed to both sets
of outputs. When EN is LOW, the Q
continue to be passed to the Q/Q ¯ outputs. The EN and SEL inputs can be driven with an ECL/PECL signal or a full supply
swing CMOS type logic signal. See table 2 for enable operation.
Internal Input biasing is accomplished with a V
V
Each Q/Q ¯ output has a 4 mA on-chip pull-down current source. External resistors may also be used to increase pull-down
current of the Q/Q ¯ to a maximum of 25mA each (includes a 4 mA on-chip current source).
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
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pin supports 1.5mA sink/source current and should be bypassed to ground with a 0.01µF capacitor.
High/Open
High/Open
Low
Low
EN
N
OTES
Q
Q
SEL
EN
D0
Q
D1
Q
Low/Open
Low/Open
HG
HG
CS-SEL
High
High
¯¯ is selected. See Table 2 for data selection.
HG
/Q ¯
HG
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Figure 2 - Timing Diagram
outputs will be forced LOW/HIGH respectively, while input data will
and separate 470Ω bias resistors connecting each data input to V
D0/D0
D1/D1
D0/D0
D1/D1
Table 2 - Truth Table
AZ100LVEL16VV
Q
¯¯
¯¯
¯¯
¯¯
3
D0/D0
D1/D1
D0/D0
D1/D1
Q ¯
¯¯
¯¯
¯¯
¯¯
Gain Stage & Buffer with Enable
Dual Frequency PECL/ECL Oscillator
D0/D0
D1/D1
Low
Low
Q
HG
¯¯
¯¯
D0/D0
D1/D1
High
High
Q ¯
HG
¯¯
¯¯
May 2012, Rev 2.0
¯¯ is selected.
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. The