ZR36057 ZORAN [Zoran Corporation], ZR36057 Datasheet
ZR36057
Related parts for ZR36057
ZR36057 Summary of contents
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... Windows 3.1 and Windows 95. T PCI motherboards with multimedia capability. T JPEG/MPEG1 solutions for PowerPC and Macintosh PCI systems. ZR36016 ZR36057 ZR36050 PCI Bus T T Santa Clara, CA 95054 (408) 986-1314 ZR36057 Video Encoder Strip Buffer 32kB SRAM Graphics Sub-System JPEG Core T FAX (408) 986-1240 August 1996 ...
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... Enhanced PCI Bus Multimedia Controller Enhanced PCI Bus Multimedia Controller Features Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction The ZR36057 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 JPEG System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Motion Video Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Motion Video Decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Still Image Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Still Image Decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Notations and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Digital Video Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Digital Video Front End (VFE) ...
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... Video Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 GuestBus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Codec Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Appendix A: ZR36100 - ZR36057 Interface 44 ZR36100 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Mapping the ZR36100 on the ZR36057’s GuestBus . . . . . . . 44 ZR36100 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Appendix B: MD207/MD208 - ZR36057 Interface 45 MD207/208 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Mapping the MD207/208 on the ZR36057 ’s GuestBus . . . . . 45 Appendix C: Fitting the Input Size to the Required Display Window 46 Calculating the Horizontal Parameters: ...
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... ZR36016. The ZR36016 performs the block-to-raster conversion and drives the video to the video encoder to be displayed monitor. The ZR36016 video output is driven simultaneously to the Video Front End of the ZR36057 to be processed the capture mode, and transferred using DMA to the PC display memory. ...
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Notations and Conventions External signals: Capital letters (e.g., IDSEL) [1] Active-low mark : Overbar (e.g., DEVSEL) Internal function units: capital (non-bold) letters (e.g., VFE) Buses: XXmsb_index..lsb_index (e.g., AD31..0) Register fields: XXmsb_index:lsb_index (e.g., Mode27:16) Register types read only ...
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... The incoming video is processed along the video path and transferred to the graphics display memory using PCI DMA bursts. The ZR36057 Video Front End samples the video bus within a programmable active field window, defined with repect to the video synchronization signals. An optional vertical and horizon- tal smooth scale down can be applied, in order to support variable image sizes and variable PCI video data rate ...
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... PCI clock. I PCI reset. When active, all ZR36057 output pins are tri-stated. A low to high transition puts the ZR36057 into its power-on reset state. Minimum active low duration is 3 PCI clocks. PCI interrupt request A. A low level on this signal requests an interrupt from the host. ...
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... Bidirectional Code DMA transfer with support for fragmented code buffers. • Control of the ZR36050/ZR36016 Motion JPEG chip set. The ZR36057 supports digital video in CCIR 601 or square pixel formats, following either the NTSC or PAL video standard. Other non-standard input schemes are supported as well. ...
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... KBytes up to 256 KBytes. The destination block may also be virtually split into several sub-blocks, allowing the ZR36057 to interrupt the host when a sub-block has been transferred. This feature provides the software with a means of optimizing the refill accesses according to the application requirements and the disk performance ...
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... Memory Read Line (PCI command 1110b), from system memory to the ZR36057’s Mask Buffer memory to the ZR36057’s Code FIFO buffer bus target, the ZR36057 responds to the following types of transfer: Memory Read Memory Read Line Memory Read Multiple ...
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... VCLK, i.e., VCLK is used as a clock qualifier. The qualifying polarity of VCLK is configured by the host. This scheme makes the ZR36057 compatible with a wide range of digital video sources and immune to board-level parasitic delays. VCLKx2 (positive edges) is used internally in the video processing pipeline ...
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... In Still Image Compression mode, the image is transferred to the ZR36057 by the host software pixel by pixel. PXEN is activated only when a pixel is ready to be sent out from the ZR36057 Video Interface to the ZR36016 video input. In Still Image Decompression mode, the image is read from the ZR36057 by the host software pixel by pixel ...
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... The protocol for a still image decompression read operation, and the ZR36057’s behavior, are as follows: • The ZR36057 checks the Still_Bsy bit meaning that the previous valid pixel was read by the host, the ZR36057 fetches a new pixel from the ZR36016. ...
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... PostOffice direction bit (PODir). The identity of the targeted guest and its specific 2. A typical choice for guest configured a priori for the code-write cycles would be a decompression device, such as the ZR36100/ ZR36110, in the ZR36057’s MPEG mode. ...
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... PostOffice Handshaking Protocol Reading data from or writing data to any of the ZR36057 guests using the PostOffice mechanism requires the host software to follow the handshaking protocol described below. The main idea is that the host has to poll the PostOffice request pending bit in order to confirm the availability of the GuestBus and verify the validity of the data contained in the PostOffice data byte ...
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... In this example, two code bytes are transferred from the ZR36057 to the ZR36050. The falling edge of CCS designates the start of the cycle. The data is driven by the ZR36057. The ZR36050 samples the data with the rising edge of COE (note that COE is not an input to the ZR36057 mentioned here only for the completeness of the description) ...
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... CCS to enable the drive of the code stream. 5.6 I2C Bus Interface 2 The I C port of the ZR36057 consists of a clock signal, SCK, and data signal, SDA. Both have two possible levels: active low or passive tri-state. This configuration lets the ZR36057 be the only master ...
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... INTA output. It stores the corresponding status bits in the Interrupt Status Register, and clears the status bits per host instructions. The ZR36057 can associate any one of the following events with an interrupt request: • A positive edge on the GIRQ1 input pin. • A positive edge on the GIRQ0 input pin. ...
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... The register description (See “Application- Specific Registers (ASRs)” on page 25) specifies the conditions under which each parameter is allowed to be modified. The ZR36057 transfers the video to a rectangle in the display (or system) memory, defined by a base address for each field (MaskTopBase, MaskBotBase), an inter-line stride (DispStride), and the rectangle height (VidWinHt) and width (VidWinWid) ...
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... Gib Endian B7...0 G7...0 8.0 GRAPHICS OVERLAY The ZR36057’s Video DMA Controller is capable of masking off (i.e., not transmitting) pixels that are marked by ‘0’ masking map prepared and maintained by the driver software. The masking feature, referred to as overlay or clipping, is turned on by setting the OvlEnable parameter to ‘1’. As long as OvlEna- ble=’ ...
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... Description • After successfully completing transfer of the compressed data of a field or frame, the ZR36057 writes the status infor- mation back to the STAT_COM entry of the current buffer. It sets the STATUS_BIT in the STAT_COM entry, declaring its content as status. It then issues an interrupt, and starts the next field or frame process. • ...
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... The Triton bit (in the Video Display Configuration Register) should be 0. This bit causes the ZR36057’s REQ signal to be de-asserted immediately after the bus was granted. Typi- cally (on machines with Triton PCI chip set), this causes the GNT signal to be de-asserted. The ZR36057’ ...
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... After the hardware reset is over, the ZR36057 will be in software reset condition until the SoftReset bit is deasserted. 10.2 Software Reset There are two ways in which the ZR36057 can go into the software reset condition: one is right after hardware reset (i.e., upon the low to high transition of PCIRST), the other is by clearing the SoftReset bit ...
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... Parity Error Response. Hardwired to ‘0’. Unused. Hardwired to ‘0’. Master Enable. When this bit is set to ‘1’ the ZR36057 can operate as a bus master. Default is ‘0’. Memory Access Enable. When this bit is set to one the device responds to PCI memory accesses. ...
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... APPLICATION-SPECIFIC REGISTERS (ASRS) The ZR36057 application-specific registers (ASRs) are memory- mapped. Their base address is configured by the host into PCI configuration address 0x10. The ZR36057 claims a contiguous range of 4K bytes of memory. PCI memory-read accesses to addresses (within the 4K range) that are not explicitly described in this section return zeros ...
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Enhanced PCI Bus Multimedia Controller 12.3 Video Front End, Scaler and Pixel Format Register This register contains the video front end configuration (byte 3), video scaler (bytes 2-1) and pixel formatter (byte 0) parameters Address Offset: 0x008 Bit Type Mod ...
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... Address Offset: 0x014 Bit Type Mod 1 RW all SnapShot - Frame Grab Mode. If this bit is asserted the ZR36057 goes into frame grab mode. When deasserted continu- ous display of video is resumed. ‘1’ - frame grab mode. ‘0’ - continuous display mode (default value snap FrameGrab - Frame Grabbing Command/ Status ...
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... Type Mod Description 23:22 R Reserved. Returns zero. 21:12 RW vid VidWinHt - Video Window Height. This register defines the number of lines that should be displayed by the ZR36057. If DispMod = 0, VidWinHt is half the number, if DispMod = the entire number of display lines. Default value is 0x0F0. 11:10 R Reserved. Returns zero. 9:0 RW vid VidWinWid - Video Window Width ...
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... Reserved. Returns zero all SoftReset - Software Reset. This bit is asserted by the host to reset the ZR36057. If this bit is set to ‘0’ all resettable registers in the device will be reset to their default value, except: - the SoftReset bit, - the PCI interface. The device continues to respond according to the PCI Specification and can be the target of a PCI transfer targeted at the ASRs or config ...
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... CodReadEn - MPEG Code-Read Enable. In MPEG mode, if this bit is cleared by the host, the code-read transfers are stopped. The current code-read pointer retains its value. When this bit is set to ‘1’, the ZR36057 resumes code-read transfers. Default value is ‘0’. 6:4 R Reserved. Returns zero. ...
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MPEG Code Memory Pointer Register This register contains the pointer to the code memory of the host in MPEG mode. Address Offset: 0x038 Bit Type Mod Description 31:16 R Unused. Returns zero. 15:0 RW cod CodMemPoint - MPEG Code ...
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Enhanced PCI Bus Multimedia Controller Address Offset: 0x040 (Continued) Bit Type Mod Description 27 RW all JPEGRepIRQEn - JPEG Report Interrupt Request Enable. When enabled and IntPinEn is set to ‘1’, an interrupt request will be gener- ated on the ...
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... Reserved. Returns zero all P_reset - Process Reset. This bit is asserted by the host in order to reset the ZR36057 JPEG-related state machines. The bit must be asserted at the beginning of a JPEG process. While it is asserted, all of the JPEG process parameters may be configured by the host. ...
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... FrmTot - Frame total size. The total number of lines per frame. This parameter must be an odd number. Default Value is 0x020D (525, for NTSC) 12.23 Horizontal Sync Parameters This register contains the HSYNC parameters to be generated by the ZR36057 as a sync master. Address Offset: 0x10C Bit Type Mod Description ...
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... When Still Image Decompression mode is selected (and after P_reset was de-assert- ed), the bit is ‘1’. After the ZR36057 fetches a new pixel, and the pixel is ready for the host to read it, the bit is reset to ‘0’ set to ‘1’ ...
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Enhanced PCI Bus Multimedia Controller 13.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Storage Temperature .........................................65°C to +150°C Supply Voltage (V ) ........................................-0 +6 Output Voltage ........................................ 0 Input Voltage.......................................... -0 ...
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AC TIMING SPECIFICATIONS 14.1 PCI Bus Timing Table 16: PCI Bus Timing Symbol Parameter t PCICLK period PCI t PCICLK high PH t PCICLK low PL t PCICLK slew rate A3 t PCICLK to signal valid delay - bussed ...
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Enhanced PCI Bus Multimedia Controller 14.2 Video Bus Timing Table 17: Video Bus Timing Symbol Parameter t VCLKx2 period V2P t VCLKx2 rise/fall transition V2T t VCLK rise/fall transition VT t Video bus input setup VIS t Video bus input ...
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... GRS t PCI PCP PD GRS RWDUR RWC t RWREC t GDH Data Valid from ZR36057 t RWDUR t DUR t GWS t GWL Figure 13. GuestBus Timing 39 Max Unit Determined by parameter T and signal GWS ns Determined by parameter Typical output load Typical output load 70 pF ...
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Enhanced PCI Bus Multimedia Controller Codec Bus Interface Timing 14.3.1 Table 20: Symbol Parameter t CCS setup CCS t CCS hold CCH t Code output propagation delay CPD t Code output hold delay CHD t Code input setup CIS t ...
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MECHANICAL DATA 15.1 Pinout Pin Pin Pin No. Pin Name No. Pin Name No. 1 VSS 27 DEVSEL 53 2 VDD 28 VSS 54 3 VSS 29 STOP 55 4 IDSEL 30 PAR 56 5 AD23 31 VSS 57 ...
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... VSS C/BE1 VDD AD15 VSS AD14 VSS AD13 AD12 VSS AD11 C/BE0 VSS VDD AD10 AD9 VSS AD8 AD7 VSS VDD VDD 52 ZR36057 (TOP VIEW) 42 156 VSS VDD VDD VSS VSS HSYNC VSYNC VDD FI PXEN RTBSY START VDD VCLK ...
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... Dimensions 157 208 Enhanced PCI Bus Multimedia Controller 31.1 ±0.4 SQ. 28.0 ±0.2 SQ. 25.5 REF. ZR36057 (Top View) Pin 1 Index 1 0.50 Nom. 0.23 ±0.08 3.4 ±0.4 0.30 ±0.05 0.8 ±0.2 Dimensions in millimeters 43 104 53 52 1.60 REF. SEATING PLANE 0~7° ...
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... Figure 15. ZR36057 - ZR36100/110 Basic Interconnection ZR36100 Reset Any of the software controlled GPI/O pins (configured as output) of the ZR36057 may be used as a RESET input of the decoder. The software then directly manipulates the RESET signal through the corresponding register bit. Since the default config- uration of the GPIO pins after reset is input, a pull down resistor should be applied to the ZR36100 RESET input ...
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... MD207/208 hardware reset is needed in the design, any of the software controlled GPI/O pins (configured as output) of the ZR36057 may be used as a RESET signal. The software then directly manipulates the RESET signal through the corresponding register bit of the ZR36057 ...
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... Enhanced PCI Bus Multimedia Controller Appendix C: Fitting the Input Size to the Required Display Window The ZR36057 can crop the input video and scale it down to match any display size required by different applications, as long as the required size is not larger than the original input. This appendix provides some programming guidelines for proper setting of the ZR36057 parameters involved in this process ...
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... DispMod!) Y and He denote two temporary variables: VStart and VEnd are then calculated from vcrop1 and vcrop2. In the example: The ZR36057 will actually sample-in 235 lines from every field. The first 2 and the last 3 active lines of every field will be cut out. 47 Ha/2 ...
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Enhanced PCI Bus Multimedia Controller ORDERING INFORMATION ZR 36057 PQ C SALES OFFICES T U.S. Headquarters Zoran Corporation 2041 Mission College Blvd Santa Clara, CA 95054 USA Telephone: 408-986-1314 FAX: 408-986-1240 Trademarks: All brand, product, and company names are trademarks ...