UT54LVDS032-UCA AEROFLEX [Aeroflex Circuit Technology], UT54LVDS032-UCA Datasheet
UT54LVDS032-UCA
Related parts for UT54LVDS032-UCA
UT54LVDS032-UCA Summary of contents
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... EN EN Figure 1. UT54LVDS032 Quad Receiver Block Diagram INTRODUCTION The UT54LVDS032 Quad Receiver is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology ...
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... Active low enable pin, OR- Power supply pin, + APPLICATIONS INFORMATION The UT54LVDS032 receiver’s intended use is primarily in an uncomplicated point-to-point configuration as is shown Figure 3. This configuration provides a clean signaling environment for quick edge rates of the drivers. The receiver is ...
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... Receiver Fail-Safe The UT54LVDS032 receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to TTL logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. The receiver’s internal fail-safe circuitry is designed to source/ ...
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ABSOLUTE MAXIMUM RATINGS (Referenced SYMBOL I/O T STG Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is ...
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DC ELECTRICAL CHARACTERISTICS (V = 5.0V +10%; -55 C < T < +125 SYMBOL PARAMETER V High-level input voltage IH V Low-level input voltage IL V Low-level output voltage OL V High-level output voltage OH I Logic ...
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AC SWITCHING CHARACTERISTICS (V = +5. +125 SYMBOL t Differential Propagation Delay High to Low PHLD CL = 20pf (figures 4 and 5) t Differential Propagation Delay Low to High ...
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Generator 5 0 Figure 4. Receiver Propagation Delay and Transition Time Test Circuit or Equivalent Circuit R IN- 0V Differential R IN+ t PLHD 1.25V R OUT 20% t TLH Figure 5. Receiver Propagation Delay and Transition Time Waveforms R ...
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EN R IN+ R IN- Figure 6. Receiver Three-State Delay Test Circuit or Equivalent Circuit EN when when Output when V = -100mV ID Output when V = +100mV ID Figure ...
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Notes: 1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to VSS. 3. Lead finishes are in accordance to MIL-PRF-38535. 4. Package dimensions and symbols are similar to MIL-STD-1835 variation ...
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... Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55 C, room temp, and 125 C. Radiation neither tested nor guaranteed. Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = Military Temperature Range flow (P) = Prototype flow Package Type: (U) = 16-lead Flatpack (dual-in-line) Access Time: Not applicable Device Type: UT54LVDS032 LVDS Receiver 10 ...
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... UT54LVDS032 QUAD RECEIVER: SMD 95834 ** * * * 5962 - Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: ( lead Flatpack (dual-in-line) Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type 02 = LVDS Receiver Drawing Number: 95834 Total Dose (R) = 1E5 rad(Si) ...