U62256ADA07 ZMD [Zentrum Mikroelektronik Dresden AG], U62256ADA07 Datasheet

U62256ADA07

Manufacturer Part Number

U62256ADA07

Description

STANDARD 32K X 8 SRAM

Manufacturer

ZMD [Zentrum Mikroelektronik Dresden AG]

Datasheet

1.U62256ADA07.pdf (10 pages)

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Features

Pin Configuration

April 20, 2004

(MIL STD 883C M3015.7)

data outputs

dissipation in long Read Cycles

32768x8 bit static CMOS RAM

Access times 70 ns, 100 ns

Common data inputs and

Three-state outputs

Typ. operating supply current

TTL/CMOS-compatible

Automatical reduction of power

Power supply voltage 5 V + 10 %

Operating temperature ranges

ESD protection > 2000 V

Latch-up immunity >100 mA

Packages: PDIP28 (600 mil)

QS 9000 Quality Standard

DQ0

DQ1

DQ2

VSS

A14

A12

100 ns: 40 mA

-40 to 85 °C

-40 to 125 °C

70 ns: 50 mA

0 to 70 °C

SOP28 (330 mil)

Top View

PDIP

SOP

VCC

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

Description

The U62256A is a static RAM

manufactured using a CMOS pro-

cess technology with the following

operating modes:

- Read

- Write

The memory array is based on a

6-transistor cell.

The circuit is activated by the fal-

ling edge of E. The address and

control inputs open simultaneously.

According to the information of W

and G, the data inputs, or outputs,

are active. In a Read cycle, the

data outputs are activated by the

falling edge of G, afterwards the

data word read will be available at

the outputs DQ0-DQ7. After the

address change, the data outputs

go High-Z until the new information

read is available. The data outputs

have not preferred state.

The Read cycle is finished by the

- Standby

- Data Retention

1 1

Signal Name

A0 - A14

DQ0 - DQ7

VCC

VSS

Pin Description

Address Inputs

Data In/Out

Signal Description

Chip Enable

Output Enable

Write Enable

Power Supply Voltage

Ground

falling edge of W, or by the rising

edge of E, respectively.

Data retention is guaranteed down

to 2 V. With the exception of E, all

inputs consist of NOR gates, so

that no pull-up/pull-down resistors

are required.

Standard 32K x 8 SRAM

U62256A

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U62256ADA07 Summary of contents

Page 1

Features 32768x8 bit static CMOS RAM ! Access times 70 ns, 100 ns ! Common data inputs and ! data outputs Three-state outputs ! Typ. operating supply current ! 70 ns 100 ns TTL/CMOS-compatible ! Automatical ...

Page 2

U62256A Block Diagram A10 A11 A12 A13 A14 Address Change Detector Truth Table Operating Mode Standby/not selected Internal Read Read Write * Memory Cell Array 512 Rows ...

Page 3

Characteristics All voltages are referenced (ground). SS All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of ...

Page 4

U62256A Electrical Characteristics Supply Current - Operating Mode Supply Current - Standby Mode (CMOS level) Supply Current - Standby Mode (TTL level) Output High Voltage Output Low Voltage Input High Leakage Current Input Low Leakage Current Output High Current Output ...

Page 5

Switching Characteristics Read Cycle Read Cycle Time Address Access Time to Data Valid Chip Enable Access Time to Data Valid Output Enable Access Time to Data Valid E HIGH to Output in High-Z G HIGH to Output in High-Z E ...

Page 6

U62256A Data Retention Mode 4 Data Retention Characteristics Data Retention Supply Voltage Data Retention Supply Current Data Retention Setup Time Operating Recovery Time Test Configuration for Functional Check measurement of t ...

Page 7

Capacitance Input Capacitance Output Capacitance All pins not under test must be connected with ground by capacitors Ordering Code Example Type Package D = PDIP28 (600 mil, only C/K-Type and SOP28 (330 mil) Type 2 Operating ...

Page 8

U62256A Read Cycle 1: Ai-controlled (during Read Cycle : DQi Output Read Cycle 2: G-, E-controlled (during Read Cycle DQi Output Address Valid t a(A) ...

Page 9

Write Cycle1: W-controlled Input DQ i Output G Write Cycle 2: E-controlled Input DQ i Output G undefined The information describes the type of component and shall not ...

Page 10

LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which ...

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