MPXD2005VLT120R FREESCALE [Freescale Semiconductor, Inc], MPXD2005VLT120R Datasheet
MPXD2005VLT120R
Related parts for MPXD2005VLT120R
MPXD2005VLT120R Summary of contents
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Freescale Semiconductor Data Sheet: Advance Information PXD20 Microcontroller Data Sheet The PXD20 represents a new generation of 32-bit microcontrollers targeting single-chip industrial HMI applications. PXD20 devices are part of the PX family of ® Power Architecture -based devices. This family ...
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Overview 1 Overview 1.1 Device comparison Feature Package CPU Execution speed Flash memory (ECC) RAM (ECC) On-chip graphics RAM (no ECC) MPU eDMA DRAM controller OpenVG Graphics Accelerator (GFX2D) Display Control Unit (DCU3) Display Control Unit Lite (DCULite) Timing Controller ...
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Table 1. PXD20 Family Feature Set (continued) Feature Package Analog-to-Digital Converter (ADC) CAN (64 mailboxes) CAN sampler Serial communication interface SPI GPIO Debug Freescale Semiconductor 176 LQFP 16 channels, 10-bit 3 × LIN 2 × SPI 128 ...
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Overview 1.2 Block diagram PXD20 Block Diagram System Debug VREG JTAG Oscillator Nexus Class 3+ FMPLL x 2 RTC/32 kHz Oscillator Interrupt 16-ch DMA Controller PIT SWT STM 2 MB Flash Boot Assist ECC Module (BAM) Crossbar Slaves Communications I/O ...
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Feature list • Dual-issue, 32-bit Power Architecture Book E compliant CPU core complex (e200z4d) — Memory Management Unit (MMU) — 4 KB, 2/4-way instruction cache • on-chip ECC flash memory with: — Flash memory controller — Prefetch ...
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Overview — Interfaces to external, memory-mapped serial flash memories — Supports simultaneous addressing of 2 external serial flashes to achieve up 80 MB/s read bandwidth • RLE decoder supporting memory to memory decoding of RLE data in conjunction with eDMA ...
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LQFP, 0.5 mm pitch outline — 416 TEPBGA, 1mm ball pitch outline 1.4 Feature details 1.4.1 Low-power operation The PXD20 is designed for optimized low-power operation and dynamic ...
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Overview SoC features RUN HALT STOP ...
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Regulates input to generate all internal supplies — Manages power gating — External ballast transistor for high power regulator — Low-Power and Ultra-Low-Power regulators support operation when in STOP and STANDBY modes, respectively, to minimize power consumption — Startup ...
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Overview • Seven master ports: — e200z4d core instruction port — e200z4d core complex load/store data port — eDMA controller — DCU — DCU-Lite — VIU — 2D Graphics Accelerator (GFX2D) • Seven slave ports: — Platform Flash Controller (2 ...
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ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. When multiple tasks share a resource, coherent accesses ...
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Overview • Direct readback of the pin value supported on all digital output pins through the SIU • Configurable digital input filter that can be applied general purpose input pins for noise elimination on external interrupts ...
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Memory Protection Unit (MPU) The MPU features the following: • Sixteen region descriptors for per master protection • Start and end address defined with 32-byte granularity • Overlapping regions supported • Protection attributes can optionally include process ID • ...
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Overview To secure the content of all critical information to be displayed, a safety mode can be activated to check the integrity of critical data along the whole system data path from the memory to the TFT pads. The DCU3 ...
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Timing controller (TCON) and RSDS interface The TCON enables direct drive of the row and column drivers of display panels enabling emulation of TCON ICs used in display panels. • Programmable Timing Generation unit featuring 12 waveform generators allowing ...
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Overview 1.4.18 Video Input Unit (VIU2) The VIU2 is a crossbar master module accepting an ITU656 compatible video input stream on a parallel interface, converting the pixel data to RGB or YUV format and transferring the video image to internal ...
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Analog-to-digital converter (ADC) The ADC features the following: • 10-bit A/D resolution • 0– 0–3.3 V common mode conversion range • Supports conversions speeds 1s • 20 internal and 8 external channels support • ...
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Overview • Programmable data frames from bits • chip select lines available, depending on package and pin multiplexing, enable 8 external devices to be selected using external muxing from a single SPI • Eight ...
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Data buffers with 4-byte receive, 4-byte transmit — Configurable word length (8-bit or 9-bit words) — Error detection and flagging – Parity, noise and framing errors — Interrupt driven operation with 4 interrupts sources — Separate transmitter and receiver ...
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Overview 1.4.26 System clocks and clock generation modules The system clock on the PXD20 can be derived from an external oscillator, an on-chip FMPLL, or the internal 16 MHz oscillator. The source system clock frequency can be changed via an ...
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Real time counter (RTC) The Real Timer Counter supports wake-up from Low Power modes or Real Time Clock generation • Configurable resolution for different timeout periods — resolution for >1 hour period — resolution for ...
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Overview 1.4.32 Stepper stall detect (SSD) module The SSD module provides a circuit to measure and integrate the induced voltage on the non-driven coil of a stepper motor using full steps when the gauge pointer is returning to zero (RTZ). ...
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Data Trace via Data Write Messaging (DWM) and Data Read Messaging (DRM). This provides the capability for the development tool to trace reads and/or writes to selected internal memory resources. • Ownership Trace via Ownership Trace Messaging (OTM). OTM ...
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Pinout and signal descriptions 2 Pinout and signal descriptions 2.1 176 LQFP package pinout Figure 2 shows the pinout for the 176-pin LQFP package. DCU_VSYNC / PG8 1 DCU_HSYNC / PG9 2 DCU_DE / PG10 3 eMIOS0[8] / eMIOS1[9] / ...
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LQFP package pinout Figure 3 shows the pinout for the 208-pin LQFP package. DCU_VSYNC_TCON2 / PG8 1 DCU_HSYNC_TCON1 / PG9 2 DCU_DE_TCON3 / PG10 3 eMIOS0[8] / eMIOS1[9] / PDI_HSYNC_VIU1 / PJ1 4 eMIOS0[9] / eMIOS1[14] / PDI_VSYNC_VIU0 ...
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TEPBGA package pinout–40 to 105°C Figure 4 shows the pinout for the 416 TEPBGA package ddr_dq[2 ddr_dq[2 ddr_dq[2 ddr_dq[2 A 30] 31] ddr_ba[0]ddr_ba[1]ddr_ba[ ddr_dq[2 ddr_dqs[ ddr_dm[3 ...
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Signal description The following sections provide signal descriptions and related information about the signals’ functionality and configuration. 2.4.1 Pad configuration during reset phases All pads have a fixed configuration under reset. During the power-up phase, all pads are forced ...
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Pinout and signal descriptions Table 3. Voltage supply pin descriptions (continued) Supply pin Function V 1.2 V ground SS VDD12 ground and VDDPLL ground (VSSPLL) V 3.3 V I/O supply. This supply is shared with DDE_B internal flash, 16 MHz ...
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Decoupling capacitors must be connected between these pins and the nearest V 2 VDDA must be at the same voltage as VDDE_A. 3 This signal needs to be connected to ground during normal operation. 2.4.3 Pad types The pads ...
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Pinout and signal descriptions 1 Reset configuration is given as I/O direction and pull direction (for example, “Input, pullup”). 2 Although this signal is not a supply for RSDS pads, it needs to be terminated in an external capacitor with ...
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System pin Function MDO[8] Nexus Msg Data Out MDO[9] Nexus Msg Data Out MDO[10] Nexus Msg Data Out MDO[11] Nexus Msg Data Out 1 On the 176 LQFP and 208 LQFP package options the Nexus pins are multiplexed with other ...
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Pinout and signal descriptions Table 6. DRAM interface pin summary (continued) 1 Port pin Function DDR_DQ[11] DRAM Data Bus [11] DDR_DQ[10] DRAM Data Bus [10] DDR_DQ[9] DRAM Data Bus [9] DDR_DQ[8] DRAM Data Bus [8] DDR_DQ[7] DRAM Data Bus [7] ...
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Table 6. DRAM interface pin summary (continued) 1 Port pin Function DDR_A[10] DRAM address [10] DDR_A[9] DRAM address [9] DDR_A[8] DRAM address [8] DDR_A[7] DRAM address [7] DDR_A[6] DRAM address [6] DDR_A[5] DRAM address [5] DDR_A[4] DRAM address [4] DDR_A[3] ...
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Pinout and signal descriptions Table 6. DRAM interface pin summary (continued) 1 Port pin Function DDR_CLKB DRAM Clock bar DDR_CK DRAM Clock Enable DDR_CS DRAM Chip Select MVREF DDR Reference Voltage MVTT DRAM Termination Voltage 1 These port pins are ...
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SGM muxing The SGM shares pins between the PWM output signals and the I2S bus signals as shown in the “Port pin summary” table. When the PWM function is enabled in the SGM (SGMCTL[PWME]) the PWM (PWMO, PWMOA) signals ...
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Functional ports The functional port pins are listed in Table 7. The following pad types are available for system pins and functional port pins: • S — Slow (pad_ssr, pad_ssr_hv) • M — Medium (pad_msr, pad_msr_hv) • F — ...
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Port Alternate PCR Function 1 pin function PA[5] PCR[5] Option 0 GPIO[5] Option 1 DCU_R5 Option 2 — Option 3 — PA[6] PCR[6] Option 0 GPIO[6] Option 1 DCU_R6 Option 2 — Option 3 — PA[7] PCR[7] Option 0 GPIO[7] ...
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Port Alternate PCR Function 1 pin function PA[14] PCR[14] Option 0 GPIO[14] Option 1 DCU_G6 Option 2 — Option 3 — PA[15] PCR[15] Option 0 GPIO[15] Option 1 DCU_G7 Option 2 — Option 3 — PORT B PB[0] PCR[16] Option ...
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Port Alternate PCR Function 1 pin function PB[6] PCR[22] Option 0 GPIO[22] Option 1 SIN_1 Option 2 MA2 Option 3 ABS[0] PB[7] PCR[23] Option 0 GPIO[23] Option 1 SIN_0 Option 2 eMIOS1[20] Option 3 I2S_SCK/PWMOA PB[8] PCR[24] Option 0 GPIO[24] ...
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Port Alternate PCR Function 1 pin function PORT C PC[0] PCR[30] Option 0 GPIO[30] Option 1 — Option 2 — Option 3 — PC[1] PCR[31] Option 0 GPIO[31] Option 1 — Option 2 — Option 3 — PC[2] PCR[32] Option ...
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Port Alternate PCR Function 1 pin function PC[9] PCR[39] Option 0 GPIO[39] Option 1 — Option 2 — Option 3 — PC[10] PCR[40] Option 0 GPIO[40] Option 1 — Option 2 I2S_DO/PWMO Option 3 — PC[11] PCR[41] Option 0 GPIO[41] ...
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Port Alternate PCR Function 1 pin function PD[2] PCR[48] Option 0 GPIO[48] Option 1 M0C1M Option 2 SSD0_2 Option 3 eMIOS1[23] PD[3] PCR[49] Option 0 GPIO[49] Option 1 M0C1P Option 2 SSD0_3 Option 3 eMIOS0[9] PD[4] PCR[50] Option 0 GPIO[50] ...
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Port Alternate PCR Function 1 pin function PD[11] PCR[57] Option 0 GPIO[57] Option 1 M2C1P Option 2 SSD2_3 Option 3 eMIOS0[11] PD[12] PCR[58] Option 0 GPIO[58] Option 1 M3C0M Option 2 SSD3_0 Option 3 eMIOS0[12] PD[13] PCR[59] Option 0 GPIO[59] ...
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Port Alternate PCR Function 1 pin function PE[3] PCR[65] Option 0 GPIO[65] Option 1 M4C1P Option 2 SSD4_3 Option 3 — PE[4] PCR[66] Option 0 GPIO[66] Option 1 M5C0M Option 2 SSD5_0 Option 3 — PE[5] PCR[67] Option 0 GPIO[67] ...
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Port Alternate PCR Function 1 pin function PF[3] PCR[73] Option 0 GPIO[73] Option 1 eMIOS1[21] Option 2 MSEO Option 3 DCULITE_B4 PF[4] PCR[74] Option 0 GPIO[74] Option 1 eMIOS1[14] Option 2 SDA_1 Option 3 DCULITE_B5 PF[5] PCR[75] Option 0 GPIO[75] ...
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Port Alternate PCR Function 1 pin function PF[12] PCR[82] Option 0 GPIO[82] Option 1 QUADSPI_IO3_A Option 2 — Option 3 MDO1 PF[13] PCR[83] Option 0 GPIO[83] Option 1 QUADSPI_IO0_A Option 2 — Option 3 MDO2 PF[14] PCR[84] Option 0 GPIO[84] ...
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Port Alternate PCR Function 1 pin function PG[4] PCR[90] Option 0 GPIO[90] Option 1 DCU_B4 Option 2 — Option 3 — PG[5] PCR[91] Option 0 GPIO[91] Option 1 DCU_B5 Option 2 — Option 3 — PG[6] PCR[92] Option 0 GPIO[92] ...
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Port Alternate PCR Function 1 pin function PG[13] — — Reserved PG[14] — — Reserved PG[15] — — Reserved PORT H 6 PH[0] PCR[99] Option 0 GPIO[99] Option 1 TCK Option 2 — Option 3 — 6 PH[1] PCR[100] Option ...
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Port Alternate PCR Function 1 pin function PH[11] — — Reserved PH[12] — — Reserved PH[13] — — Reserved PH[14] — — Reserved PH[15] — — Reserved PORT J PJ[0] PCR[105] Option 0 GPIO[105] Option 1 DCULITE_B6 Option 2 — ...
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Port Alternate PCR Function 1 pin function PJ[7] PCR[112] Option 0 GPIO[112] Option 1 VIU5_PDI3 Option 2 eMIOS0[18] Option 3 eMIOS0[14] PJ[8] PCR[113] Option 0 GPIO[113] Option 1 VIU6_PDI4 Option 2 eMIOS0[17] Option 3 eMIOS0[13] PJ[9] PCR[114] Option 0 GPIO[114] ...
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Port Alternate PCR Function 1 pin function PORT K PK[0] PCR[121] Option 0 GPIO[121] Option 1 eMIOS1[18]] Option 2 — Option 3 — PK[1] PCR[122] Option 0 GPIO[122] Option 1 QUADSPI_IO2_B Option 2 eMIOS1[14] Option 3 VIU7_PDI15 PK[2] PCR[123] Option ...
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Port Alternate PCR Function 1 pin function PK[8] PCR[129] Option 0 GPIO[129] Option 1 TXD_2 Option 2 DCULITE_R3 Option 3 TCON[9] PK[9] PCR[130] Option 0 GPIO[130] Option 1 I2S_DO / PWMO Option 2 DCULITE_R4 Option 3 TCON[10] PK[10] PCR[131] Option ...
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Port Alternate PCR Function 1 pin function PL[3] PCR[136] Option 0 GPIO[136] Option 1 — Option 2 CANTX_0 Option 3 eMIOS1[23] PL[4] PCR[137] Option 0 GPIO[137] Option 1 CS2_2 Option 2 VIU5_PDI13 Option 3 TCON[6] PL[5] PCR[138] Option 0 GPIO[138] ...
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Port Alternate PCR Function 1 pin function PL[12] PCR[145] Option 0 GPIO[145] Option 1 eMIOS1[12] Option 2 DCULITE_G4 Option 3 — PL[13] PCR[146] Option 0 GPIO[146] Option 1 eMIOS1[13] Option 2 DCULITE_G5 Option 3 — PL[14] — — Reserved PL[15] ...
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Port Alternate PCR Function 1 pin function PM[6] PCR[153] Option 0 GPIO[153] Option 1 VIU6_PDI14 Option 2 eMIOS1[23] Option 3 DCULITE_TAG PM[7] PCR[154] Option 0 GPIO[154] Option 1 VIU8_PDI16 Option 2 I2S_DO / PWMO Option 3 eMIOS1[16] PM[8] PCR[155] Option ...
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Port Alternate PCR Function 1 pin function PORT N PN[0] PCR[161] Option 0 GPIO[161] Option 1 DCULITE_HSYNC Option 2 — Option 3 TCON[4] PN[1] PCR[162] Option 0 GPIO[162] Option 1 DCULITE_VSYNC Option 2 — Option 3 TCON[5] PN[2] PCR[163] Option ...
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Port Alternate PCR Function 1 pin function PN[8] PCR[169] Option 0 GPIO[169] Option 1 DCULITE_R6 Option 2 — Option 3 TCON[10] PN[9] PCR[170] Option 0 GPIO[170] Option 1 DCULITE_R7 Option 2 — Option 3 TCON[11] PN[10] PCR[171] Option 0 GPIO[171] ...
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Port Alternate PCR Function 1 pin function PP[1] PCR[178] Option 0 GPIO[178] Option 1 DCULITE_G7 Option 2 — Option 3 eMIOS0[22] PP[2] PCR[179] Option 0 GPIO[179] Option 1 DCULITE_B0 Option 2 CANRX_2 Option 3 VIU4_PDI12 PP[3] PCR[180] Option 0 GPIO[180] ...
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Port Alternate PCR Function 1 pin function PP[12] — — Reserved PP[13] — — Reserved PP[14] — — Reserved PP[15] — — Reserved 1 Alternate functions are chosen by setting the values of the PCR[PA] bitfields inside the SIUL module. ...
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System design information 3 System design information 3.1 Power-up sequencing The preferred power-up sequence for PXD20 is as follows: 1. Generic IO supplies or noise-free supplies, consisting of: — VDDA — VDDE_A — VDDE_B — VDDM — VDD_DR — VDD33_DR ...
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All 3.3V supplies (VDDE_B and VDD33_DR) should be ramped up first, and then the rest of the I/O supplies should be ramped up (VDDA, VDDE_A, VDDM, and VDD_DR). 3. VDDR, the regulator input supply, should be the last supply ...
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Electrical characteristics 4 Electrical characteristics 4.1 Introduction This section contains electrical characteristics of the device as well as temperature and power considerations. This product contains devices to protect the inputs against damage due to high static voltages. However ...
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Absolute maximum ratings Symbol Voltage on VDDA pin (ADC reference) with DDA respect to ground ( Voltage on VSSA (ADC reference) pin with SSA respect Voltage on ...
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Electrical characteristics Stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational ...
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V 10 F capacitance must be connected between cannot be used to drive any external component. DD12 supply pair should have a 10 F capacitor. Absolute combined ...
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Electrical characteristics Table 11. Recommended operating conditions (5.0 V) (continued) Symbol C Parameter Voltage on VDDMA (stepper motor supply) DDM pin with respect to ground ( Voltage on V DD_DR DD_DR V D Voltage ...
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Table 12. Thermal characteristics for 176-pin LQFP Symbol C Junction to Package Top Natural Convec tion 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. 2 Junction-to-Ambient Thermal ...
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Electrical characteristics Table 14. Thermal characteristics for 416-pin TEPBGA Symbol C Junction to Package Top Natural Convec tion 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. 2 ...
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At a known board temperature, the junction temperature is estimated using the following equation: where board temperature for the package perimeter ( junction-to-board thermal resistance ( power dissipation in the package (W) ...
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Electrical characteristics Semiconductor Equipment and Materials International 805 East Middlefield Rd. Mountain View, CA 94043 (415) 964-5111 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at ...
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For the PXD20 microcontroller, 100 nF should be placed between each V pair. Additionally, 10 F should be placed between the DDPLL SSPLL ...
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Electrical characteristics 1 Time after the input supply to the voltage regulator has ramped up (VDDR) and the voltage regulator has asserted the Power OK signal. Table 17. Low-power voltage regulator electrical characteristics Symbol Junction temperature ...
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Table 19. Low voltage monitor electrical characteristics Symbol Power-on reset threshold PORH LVDHV3 low voltage detector high threshold LVDHV3H LVDHV3 low voltage detector low threshold LVDHV3L LVDHV5 ...
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Electrical characteristics Table 20. DC electrical characteristics (continued) Symbol C Parameter STANDBY2 mode DDSTDBY2 8 current D (64K SRAM on STANDBY1 mode DDSTDBY1 ...
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Flash in Low Power. RCOSC 128 kHz and RCOSC 16 MHz ON. 10 MHz XTAL clock. FlexCAN: instances: 0, 1ON (clocked but no reception or transmission), LINFLEX: instances (clocked but no reception or transmission). eMIOS: ...
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Electrical characteristics Table 21. DC electrical specifications (continued) Symbol C Parameter Vol SR P Output low voltage Voh_pci SR P PCI output high voltage Vol_pci SR P PCI output low voltage Vol_fod_h SR P Fast open-drain output low voltage Pad ...
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DC specification for CMOS090LP2fg library @ VDDE = 5.0 V These pad specifications are applicable for pads in the Analog segment Only. See the “GPIO power bank supplies and functionality” table in the “Voltage Regulators and Power Supplies” chapter ...
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Electrical characteristics Table 24. DC electrical specifications (continued) Symbol C Parameter Rtgate SR D Pad_tgate_hv input resistance pupd_rm SR D pad_pupd_hv resistance mismatch pupd_leak SR D pad_pupd_hv leakage current pupd200k SR D pad_pupd_hv 200 k resistance pupd100k SR D pad_pupd_hv ...
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Table 25. DC electrical specifications (continued) Symbol Parameter Ioh_msr SR pad_msr_hv Ioh Iol_msr SR pad_msr_hv Iol Ioh_ssr SR pad_ssr_hv Ioh Iol_ssr SR pad_ssr_hv Iol Ioh_multv_h SR pad_multv_hv Ioh s Iol_multv SR pad_multv_hv Iol Rtgate SR Pad_tgate_hv input resistance pupd_rm SR ...
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Electrical characteristics Pad pad_esdspacer_hv pad_tgate_hv pad_vdd33_hv pad_vdde_hv pad_vddint3v_hv pad_vddint_hv pad_vss_hv pad_vsse_hv pad_vssint3v_hv pad_vssint_hv spcr_17_82_hv spcr_35_84_hv spcr_71_88_hv spcr_143_38_hv spcr_vdde_lvl_hv Cell Period (ns) 2 pad_msr_hv 24 62 317 425 2 pad_ssr_hv 37 130 650 840 1 All loads are lumped loads. 2 ...
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DC specification for CMOS090_ddr library @ VDDE = 3.3 V Table 28. DC electrical specifications at 3.3 V VDDE Symbol Vdd SR Core supply voltage Vdde SR I/O supply voltage Vdd33 SR I/O pre-driver supply voltage Vref SR Input ...
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Electrical characteristics Table 30. DC electrical specifications at 2.5 V VDDE (continued) Symbol C Vih SR P Input high voltage Vil SR P Input low voltage Voh SR P Output high voltage Vol SR P Output low voltage Table 31. ...
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Table 33. Output drive current @ VDDE = 1.8 V (±100mV) (continued) Pad Drive mode pad_st_dq P pad_st_clk P Symbol C Parameter Rtt SR C Effective impedance value Table 35. core_v_det_odt and core_v_det33_odt specifications VDDE C VDD 3.5 C Rising ...
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Electrical characteristics 4.9 RESET electrical characteristics The device implements a dedicated bidirectional RESET pin. V RESET filtered by filtered by lowpass filter hysteresis W 84 Figure 9. Start-up reset requirements unknown reset filtered by ...
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Symbol C Parameter Input High Level CMOS IH Schmitt Trigger Input low Level CMOS IL Schmitt Trigger Input hysteresis CMOS HYS Schmitt Trigger Output low level ...
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Electrical characteristics 4.10 Fast external crystal oscillator (4–16 MHz) electrical characteristics This device implements the fast external oscillator (FXOSC) using a low power Loop Controlled Pierce Oscillator (LCP) configuration. Table 37. Fast external crystal oscillator electrical characteristics Symbol Parameter f ...
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Slow external crystal oscillator (32 KHz) electrical characteristics The device provides a slow external oscillator/resonator driver (SXOSC). The 32 KHz oscillator operates at 32,768 Hz. PC[15] PC[14] DEVICE Figure 11. Crystal oscillator and resonator connection scheme PC[14]/PC[15] must not ...
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Electrical characteristics Table 38. Slow external crystal oscillator electrical characteristics Symbol C Parameter Oscillator frequency XOSCLP Oscillation amplitude XOSCLP Oscillator consumption XOSCLP Oscillator start-up time ...
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Data based on device simulation sys clock required for generation of DDR timing 125 MHz can be achieved only at temperatures up to 105 °C with a maximum FM depth of 2%. CPU 7 ...
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Electrical characteristics 4.15 Flash memory electrical characteristics Symbol C Parameter T C Double Word (64 bits) Program Time dwprogram Block Pre-program and Erase Time 16kpperase Block Pre-program and Erase Time 32kpperase T ...
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ADC parameters The device provides a 10-bit Successive Approximation Register (SAR) Analog to Digital Converter. 1023 1022 1021 1020 1019 1018 code out Offset Error OSE Figure 13. ...
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Electrical characteristics A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the value of source impedance of the transducer ...
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EXTERNAL CIRCUIT Source Source Impedance S R Filter Resistance F C Filter Capacitance F R Current Limiter Resistance L R Channel Selection Switch Impedance (two contributions Sampling Switch Impedance AD C ...
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Electrical characteristics The charge of C and C is redistributed also according to Equation 8: • A second charge transfer involves also again considering the worst case in which C L would be ...
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Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter according to the Nyquist theorem the conversion rate f than or at least equal to twice the conversion period ...
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Electrical characteristics Table 44. ADC electrical characteristics (continued) Symbol C Parameter ADC input sampling S capacitance ADC input pin P1 capacitance ADC input pin P2 capacitance 2 ...
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AC specifications 4.17.1 AC specification for CMOS090LP2 library @ VDDE = 3.3 V Table 45. Functional pad type AC specifications Name C pad_ssr C pad_fc C pad_msr C 1 L>H signifies low-to-high propagation delay and H>L signifies high-to-low propagation ...
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Electrical characteristics 4.17.2 AC specification for CMOS090LP2fg library @ VDDE = 5.0 V Table 46. Functional pad type AC specifications Name C 2 pad_msr_hv C 4 ...
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Table 47. Functional pad AC type specifications (continued) Name pad_ssr_hv 9 162 / 168 216 / 205 pad_i_hv 0.5 / 0.5 4.17.4 Pad AC specifications (3.3 V, PAD3V5V = ...
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Electrical characteristics 4.17.5 AC specification for CMOS090_ddr library @ VDDE = 3.3 V Prop. delay (ns) L>H / H>L Name C Min pad_st_acc C 1.4/1.4 1.7/1.7 pad_st_dq C 1.4/1.4 1.7/1.7 pad_st_clk C 1.4/1.4 1.6/1.6 4.17.6 AC specification for CMOS090_ddr library ...
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AC specification for CMOS090_ddr library @ VDDE = 1.8 V Table 51. AC electrical specifications at 1.8 V VDD Prop. delay (ns) L>H / H>L Name C Min pad_st_acc C 1.4/1.4 1.7/1.7 1.4/1.5 1.7/1.7 1.4/1.5 1.7/1.7 1.4/1.5 1.7/1.8 pad_st_dq ...
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Electrical characteristics 4.18 AC timing 4.18.1 IEEE 1149.1 interface timing Num Symbol TCK Cycle Time JCYC TCK Clock Pulse Width (Measured at V JDC ...
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TCK TMS, TDI TDO Freescale Semiconductor Figure 19. JTAG test access port timing PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Electrical characteristics 6 8 103 ...
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Electrical characteristics TCK 9 Output Signals 10 Output Signals Input Signals 104 12 Figure 20. JTAG boundary scan timing PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice 11 13 Freescale Semiconductor ...
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Nexus debug interface Num Symbol MCKO Cycle Time MCYC MCKO Duty Cycle MDC MCKO Low to MDO Data Valid MDOV ...
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Electrical characteristics TCK TCK TMS, TDI TDO 4.18.3 Interface to TFT LCD panels (DCU3 and DCULite) Figure 24 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with positive polarity. ...
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PCLK latches data into the panel on its positive edge (when positive polarity is selected). In active mode, PCLK runs continuously. This signal frequency could be from MHz depending on the panel type. • HSYNC causes ...
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Electrical characteristics Table 54. LCD interface timing parameters—horizontal and vertical Num Symbol Display pixel clock period PCP HSYNC pulse width PWH HSYNC back porch ...
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PWV Start of Frame t HCP HSYNC LD[23:0] Invalid Data (Line Data) HSYNC DE 4.18.3.2 Interface to TFT LCD panels—access level Table 55. LCD interface timing parameters Num Symbol PDI Clock Period CKP ...
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Electrical characteristics HSYNC VSYNC DDE PCLK t CKH LD[23:0] Figure 27. LCD Interface timing parameters—access level 4.18.4 RSDS interface to TFT LCD panels Symbol C Parameter AVDD SR P Voltage on VSSE_A pin with respect to ground ( ...
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Freescale Semiconductor Figure 28. TCON/RSDS timing diagram PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Electrical characteristics 111 ...
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Electrical characteristics 4.18.5 DRAM interface DDR Interface specification from ‘MCD — 32 Bit Automotive MCU — CMOS090LP2’ I/O Pad Specification Revision 1.5 — May14th 2008. This device supports SDR, DDR1, DDR2 half and full strengths, as well as LPDDR half ...
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Measured with clock pin loaded with differential 100 ohm termination resistor. 5 All transitions measured at mid-supply (V 6 Measured with all outputs except the clock loaded with 50 ohm termination resistor this window, the ...
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Electrical characteristics ipp_do pad_st/pad_st_odt 4.18.5.2 1.8V DDR2 Table 60. SSTL_18 Class II 1.8V DDR2 DC specifications Symbol C Parameter Vddet P I/O Supply Voltage Vdd P Core Supply Voltage Vref(dc) P Input Reference Voltage Vtt P Termination Voltage V C ...
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Vtt (0.5 Figure 30 (SSTL_18 Class II test load). ipp_do pad_st/pad_st_odt 4.18.5.3 1.8V LPDDR Symbol C Parameter vddet P I/O Supply Voltage vdd P Core Supply Voltage Data Inputs (DQ, DM, ...
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Electrical characteristics 4.18.6 Video Input Unit timing Clock Data Parameter C Description f D VIU2 pixel clock frequency PIX_CK t D VIU2 data setup time DSU t D VIU2 data hold time DHD 4.18.7 External Interrupt (IRQ) and Non-Maskable Interrupt ...
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Num Symbol eMIOS Input Pulse Width MIPW eMIOS Output Pulse Width MOPW 1 eMIOS timing specified MHz, V SYS ...
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Electrical characteristics Num Symbol Data Setup Time for Inputs SUI Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = ...
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PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) SIN SOUT Figure 33. DSPI classic SPI timing — Master, CPHA = 0 PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) SIN SOUT Figure 34. DSPI classic SPI timing — Master, CPHA = 1 ...
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Electrical characteristics PCSx SCK Input (CPOL=0) SCK Input (CPOL=1) SOUT SIN Figure 35. DSPI classic SPI timing — Slave, CPHA = 0 PCSx SCK Input (CPOL=0) SCK Input (CPOL=1) SOUT SIN Figure 36. DSPI classic SPI timing — Slave, CPHA ...
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PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) SIN SOUT Figure 37. DSPI modified transfer format timing — Master, CPHA = 0 PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) SIN SOUT Figure 38. DSPI modified transfer format timing — Master, CPHA ...
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Electrical characteristics PCSx SCK Input (CPOL=0) SCK Input (CPOL=1) SOUT SIN Figure 39. DSPI modified transfer format timing — Slave, CPHA = 0 PCSx SCK Input (CPOL=0) SCK Input (CPOL=1) SOUT SIN Figure 40. DSPI modified transfer format timing — ...
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I C timing Table 67. I Num Symbol — Start condition hold time 1 2 — Clock low time 1 4 — Data hold time 1 6 — CC ...
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Electrical characteristics 2 SCL 1 SDA 4.18.12 QuadSPI timing The following notes apply to Table 69 • All data is based on a negative edge data launch from PXD20 and a positive edge data capture, as shown in the timing ...
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Number SCK SCK Last address out 2. Address captured at flash 3. Data out from flash 4. Ideal data capture edge 5. Delayed data capture ...
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Electrical characteristics 70% VDDE 30% 4.18.13 TCON/RSDS timing The following notes apply to Table 71: • Measurement condition: Vdde/Vdd33 = 3.3 V ± 10%, Vdd = 1.2 V ± 10%, Vss/Vsse = –40 to 105°C Termination: ...
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Freescale Semiconductor Figure 45. Rise/fall transition, part 1 Figure 46. Rise/fall transition, part –V OD Figure 47. Illustration of tr, tf, and V PXD20 Microcontroller Data Sheet, Rev. ...
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Package mechanical data 5 Package mechanical data 6 Ordering information Tape and reel indicator Qualification status P = Pre-qualification (engineering samples Fully spec. qualified, general market flow S = Fully spec. qualified, automotive flow Temperature range V = ...
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Revision history Revision Date 1 30 Sep 2011 Initial release Apr 2012 Editorial updates and improvements throughout the document Freescale Semiconductor Table 73. Revision history ...
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