EP2S15 ALTERA [Altera Corporation], EP2S15 Datasheet - Page 228

• Manufacturer Part Number: EP2S15
• Description: Stratix II Device Family
• Manufacturer: ALTERA [Altera Corporation]

PLL Timing Specifications
5–92
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
t
t
f
f
f
f
% spread
t
t
t
L O C K
D L O C K
S W I T C H OV E R
C L B W
V C O
S S
P L L _ P S E R R
A R E S E T
A R E S E T _ R E C O N F I G
Table 5–92. Enhanced PLL Specifications (Part 2 of 2)
Limited by I/O f
If the counter cascading feature of the PLL is utilized, there is no minimum output clock frequency.
Name
Table
5–92:
M A X
Time required for the
PLL to lock from the
time it is enabled or
the end of device
configuration
Time required for the
PLL to lock
dynamically after
automatic clock
switchover between
two identical clock
frequencies
Frequency range
where the clock
switchover performs
properly
PLL closed-loop
bandwidth
PLL VCO operating
range for –3 and –4
speed grade devices
PLL VCO operating
range for –5 speed
grade devices
Spread-spectrum
modulation frequency
Percent down spread
for a given clock
frequency
Accuracy of PLL
phase shift
Minimum pulse width
on
Minimum pulse width
on the
when using PLL
reconfiguration. Reset
the PLL after
scandone
high.
. See
areset
Description
areset
Table 5–78 on page 5–69
goes
signal.
signal
0.13
Min
300
300
100
500
0.4
10
4
for the maximum. Cannot exceed f
0.03
1.20
Typ
0.5
16.90
1,040
Max
±15
500
840
500
0.6
1
1
O U T
specification.
Altera Corporation
May 2007
MHz
MHz
MHz
MHz
Unit
kHz
ms
ms
ps
ns
ns
%