PL133-37 PhaseLink Corp., PL133-37 Datasheet - Page 2

• Manufacturer Part Number: PL133-37
• Description: Low-power, 1.62v To 3.63v, 1mhz To 150mhz, 1 3 Fanout Buffer Ic
• Manufacturer: PhaseLink Corp.

PIN DESCRIPTION
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper ter-
mination this will cause reflections (looks like ringing).
- Design long traces as “striplines” or “microstrips” with
defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
2880 Zanker Rd., San Jose, California 95134
Name
CLK1
CLK0
CLK2
GND
VDD
FIN
Low-Power, 1.62V to 3.63V, 1MHz to 150MHz, 1:3 Fanout Buffer IC
(Typical buffer impedance 20Ω)
CMOS Output Buffer
Package Pin #
SOT23-6L
1
2
3
4
5
6
Place Series Resistor as close as possible to CMOS output
Use value to match output buffer impedance to
50Ω trace. Typical value 30Ω
Type
Typical CMOS termination
O
O
O
P
P
I
Tel [phone] Fax [phone]
Series Resistor
Output clock
Ground connection
Reference clock input
Output clock
Power supply
Output clock
Decoupling and Power Supply Considerations
- Place decoupling capacitors as close as possible to
the V
- Multiple V
for best performance.
- Addition of a ferrite bead in series with V
help prevent noise from other board sources
- Value of decoupling capacitor is frequency depen-
dant. Typical value to use is 0.1 F.
DD
50Ω line
pin(s) to limit noise from the power supply
Description
DD
pins should be decoupled separately
www.phaselink.com Rev 03/18/11 Page 2
To CMOS Input
PL133-37
DD
can