AT25010N-10SA-2.7C Atmel, AT25010N-10SA-2.7C Datasheet - Page 7

• Manufacturer Part Number: AT25010N-10SA-2.7C
• Manufacturer: Atmel

Functional
Description
3259C–SEEPR–06/03
The AT25010/020/040 is designed to interface directly with the synchronous serial
peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers.
The AT25010/020/040 utilizes an 8-bit instruction register. The list of instructions and
their operation codes are contained in Table 1. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low CS transition.
Table 1. Instruction Set for the AT25010/020/040
Note:
WRITE ENABLE (WREN): The device will power up in the write disable state when
V
Enable instruction. The WP pin must be held high during a WREN instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write
Disable instruction disables all programming modes. The WRDI instruction is indepen-
dent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides
access to the status register. The READY/BUSY and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the Block Write Protection bits
indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 2. Status Register Format
Table 3. Read Status Register Bit Definition
Instruction Name
WREN
WRDI
RDSR
WRSR
READ
WRITE
Bit
Bit 0 (RDY)
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Bits 4-7 are 0s when device is not in an internal write cycle.
Bits 0-7 are 1s during an internal write cycle.
CC
Bit 7
is applied. All programming instructions must therefore be preceded by a Write
X
“A” represents MSB address bit A8.
Bit 6
X
Instruction Format
0000 X110
0000 X100
0000 X101
0000 X001
0000 A011
0000 A010
Bit 5
X
Definition
Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the
write cycle is in progress.
Bit 1 = 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates
the device is WRITE ENABLED.
See Table 4.
See Table 4.
Bit 4
X
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
Bit 3
BP1
AT25010/020/040
Bit 2
BP0
Bit 1
WEN
Bit 0
RDY
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