P701-13SCL PhaseLink Corp., P701-13SCL Datasheet - Page 4

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P701-13SCL

Manufacturer Part Number
P701-13SCL
Description
Low Emi Spread Spectrum Multiplier Clock
Manufacturer
PhaseLink Corp.
Datasheet
3. TIMING CHARACTERISTICS
FUNCTIONAL DESCRIPTION
Selectable spread spectrum and modulation rates
The PLL701-13 provides selectable multiplication factor, as well as selectable modulation rate. Selection is made
by connecting pins 2 (S2), 3 (S1), 4 (S0), and 7 (S3) to a logical “zero” or “one”, according to the output clock
selection table on page 1.
Default values for S(0:3) through internal pull-up and pull-down resistor
Selection pins S0 and S3 have an internal pull-down resistor of 30kΩ, pins 2 and 3 (S1 and S2) have an internal
pull-up resistor of 30kΩ. This internal pull-down (or pull-up) resistor will pull the input value to a logical “zero” (or
“one” respectively) by default, i.e. when the pin is not connected to GND (VDD respectively). In order to override
the internal pull-up (pull-down), the pin has to be connected to VDD (GND respectively).
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
Rise Time
Fall Time
Output Duty Cycle
Input to Output Delay
Cycle to Cycle Jitter
PARAMETERS
SYMBOL
Tcyc-cyc
DT
Tr
Tf
Measured at 0.8V ~ 2.0V @ 3.3V
Measured at 2.0V ~ 0.8V @ 3.3V
Over output frequency range @ 3.3V
Low EMI Spread Spectrum Multiplier Clock
CONDITIONS
www.phaselink.com
MIN.
0.78
0.8
45
2
TYP.
0.95
0.85
PLL701-13
50
Rev 09/15/06 Page 4
MAX.
100
1.1
0.9
55
4
UNITS
ns
ns
ns
ps
%

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