74F153SJX Fairchild Semiconductor, 74F153SJX Datasheet - Page 2

• Manufacturer Part Number: 74F153SJX
• Description: MULTIPLEXER DUAL 4INPUT 16SOP
• Manufacturer: Fairchild Semiconductor
• Series: 74Fr
• Type: Multiplexerr

Specifications of 74F153SJX

• Circuit: 2 x 4:1
• Independent Circuits: 1
• Current - Output High, Low: 1mA, 20mA
• Voltage Supply Source: Single Supply
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (5.3mm Width), 16-SO, 16-SOEIIJ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Unit Loading/Fan Out
Truth Table
H
L
X
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
LOW
HIGH Voltage Level
Immaterial
Select Inputs
S
H
H
H
H
X
L
L
L
L
0
S
X
H
H
H
H
L
L
L
L
1
I
I
S
E
E
Z
Z
0a
0b
0
a
b
a
b
Pin Names
, S
–I
–I
E
H
L
L
L
L
L
L
L
L
3a
3b
1
Inputs (a or b)
I
X
H
X
X
X
X
X
X
L
0
I
H
X
X
X
L
X
X
X
X
1
Side A Data Inputs
Side B Data Inputs
Common Select Inputs
Side A Enable Input (Active LOW)
Side B Enable Input (Active LOW)
Side A Output
Side B Output
I
H
X
X
X
X
X
X
X
L
2
I
X
X
X
X
X
X
X
H
L
3
Description
Output
H
H
H
H
Z
L
L
L
L
L
2
Functional Description
The F153 is a dual 4-input multiplexer. It can select two bits
of data from up to four sources under the control of the
common Select inputs (S
circuits have individual active LOW Enables (E
can be used to strobe the outputs independently. When the
Enables (E
Z
of a 2-pole, 4-position switch, where the position of the
switch is determined by the logic levels supplied to the two
Select inputs. The logic equations for the outputs are as
follows:
The F153 can be used to move data from a group of regis-
ters to a common output bus. The particular register from
which the data came would be determined by the state of
the Select inputs. A less obvious application is as a func-
tion generator. The F153 can generate two functions of
three variables. This is useful for implementing highly irreg-
ular random logic.
b
) are forced LOW. The F153 is the logic implementation
a
HIGH/LOW
Z
Z
, E
a
b
50/33.3
50/33.3
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
U.L.
b
) are HIGH, the corresponding outputs (Z
E
I
E
I
2a
2b
a
b
•(I
•(I
•S
•S
0a
0b
1
1
•S
•S
•S
•S
0
0
0
1
1
, S
•S
•S
Output I
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
I
I
Input I
1 mA/20 mA
1 mA/20 mA
0
3a
0
3b
1
). The two 4-input multiplexer
•S
•S
I
I
1a
1b
1
1
•S
•S
•S
•S
IH
OH
0
0
/I
1
1
)
)
/I
IL
•S
•S
OL
0
0
a
, E
b
) which
a
,