SST39VF200A-70-4I-EKE-T Microchip, SST39VF200A-70-4I-EKE-T Datasheet
SST39VF200A-70-4I-EKE-T
Related parts for SST39VF200A-70-4I-EKE-T
SST39VF200A-70-4I-EKE-T Summary of contents
Page 1
... The SST39LF200A/400A/800A write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF200A/400A/ 800A write (Program or Erase) with a 2.7-3.6V power supply. These devices con- form to JEDEC standard pinouts for x16 memories. ...
Page 2
... CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF200A/400A/800A write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF200A/400A/800A write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x16 memories ...
Page 3
... Figure 2: Pin Assignments for 48-Lead TSOP © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A X-Decoder Address Buffer Latches CE# Control Logic OE# WE# SST39LF/VF200A A15 1 A14 2 A13 3 A12 4 ...
Page 4
... A17 Figure 3: Pin Assignments for 48-Ball TFBGA © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A TOP VIEW (balls facing down) SST39LF/VF200A 6 A13 A12 A14 A15 A16 A10 A11 ...
Page 5
... A Microchip Technology Company Figure 4: Pin Assignments for 48-Ball WFBGA and 48-Bump XFLGA © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A TOP VIEW (balls facing down) SST39VF200A WE ...
Page 6
... SST39LF/VF200A © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A Functions To provide memory addresses. During Sector-Erase A select the sector. During Block-Erase A block. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. ...
Page 7
... The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Read The Read operation of the SST39LF200A/400A/800A and SST39VF200A/400A/800A is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins ...
Page 8
... If both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. Data# Polling (DQ When the SST39LF200A/400A/800A and SST39VF200A/400A/800A are in the internal Program oper- ation, any attempt to read DQ ation is completed, DQ ...
Page 9
... SDP command sequence. Common Flash Memory Interface (CFI) The SST39LF200A/400A/800A and SST39VF200A/400A/800A also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as Software ID Entry command with 98H (CFI Query command) to address 5555H in the last byte sequence ...
Page 10
... A = Most significant address for SST39LF/VF200A -DQ can Program word address © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A CE# OE# WE ...
Page 11
... Refer to CFI publication 100 for more details. Table 6: System Interface Information for SST39LF200A/400A/800A and SST39VF200A/ 400A/800A Address Data 1BH 0027H 0030H 1CH 0036H 1DH 0000H 1EH 0000H 1FH ...
Page 12
... Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A Data N 18 Device size = 2 Byte (12H = 18; 2 Flash Device Interface description; 0001H = x16-only asynchronous interface Maximum number of bytes in multi-byte write = 2 Number of Erase Sector/Block sizes supported by device Sector Information ( Number of sectors ...
Page 13
... Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A Data N 20 Device size = 2 Bytes (14H = 20; 2 Flash Device Interface description; 0001H = x16-only asynchronous interface Maximum number of bytes in multi-byte write = 2 Number of Erase Sector/Block sizes supported by device Sector Information ( Number of sectors ...
Page 14
... Range Commercial Industrial Table 10:AC Conditions of Test Input Rise/Fall Time 1. See Figures 16 and 17 © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A = 25° 1. 260°C for 10 seconds Ambient Temp 0°C to +70°C Ambient Temp 0° ...
Page 15
... A sector- or block-level rating would END result in a higher minimum specification. © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A = 3.0-3.6V for SST39LF200A/400A/800A and DD Limits Min Max ...
Page 16
... Output Hold from Address Change OH 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A = 3.0-3. 2.7-3. Data Sheet ...
Page 17
... Chip-Erase SCE 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A 17 Data Sheet Min Max Units 20 µ ...
Page 18
... Note: Figure 5: Read Cycle Timing Diagram ADDRESS A MS-0 WE# OE# CE# DQ 15-0 Note: Figure 6: WE# Controlled Program Cycle Timing Diagram © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A OLZ CLZ HIGH-Z ...
Page 19
... Figure 7: CE# Controlled Program Cycle Timing Diagram ADDRESS A MS-0 CE# OE# WE Note: Figure 8: Data# Polling Timing Diagram © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A 5555 2AAA 5555 ADDR CPH T AS ...
Page 20
... Note: Figure 9: Toggle Bit Timing Diagram ADDRESS A MS-0 CE# OE# WE# DQ 15-0 Figure 10:WE# Controlled Chip-Erase Timing Diagram © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A OEH Most significant address for SST39LF/VF200A, A ...
Page 21
... Figure 11:WE# Controlled Block-Erase Timing Diagram ADDRESS A MS-0 CE# OE# WE# DQ 15-0 Figure 12:WE# Controlled Sector-Erase Timing Diagram © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A SIX-BYTE CODE FOR BLOCK-ERASE 5555 2AAA 5555 5555 T WP XXAA XX55 XX80 XXAA ...
Page 22
... Figure 13:Software ID Entry and Read ADDRESS A 14-0 CE# OE# WE# DQ 15-0 Figure 14:CFI Query Entry and Read © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY 5555 2AAA 5555 IDA T WPH ...
Page 23
... A Microchip Technology Company ADDRESS A 14-0 DQ 15-0 CE# OE# WE# Figure 15:Software ID Exit/CFI Exit © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET 5555 2AAA 5555 XXAA XX55 XXF0 T IDA T ...
Page 24
... V and fall times (10% Figure 16:AC Input/Output Reference Waveforms Figure 17:A Test Load Example © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A V INPUT REFERENCE POINTS IT (0 for a logic “1” and V ...
Page 25
... A Microchip Technology Company Figure 18:Word-Program Algorithm © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A Start Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XXA0H Address: 5555H Load Word ...
Page 26
... Initiated Wait SCE Program/Erase Completed Figure 19:Wait Options © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A Toggle Bit Program/Erase Initiated Read word Read same word No Does DQ 6 match Yes ...
Page 27
... Wait T IDA Read CFI data Figure 20:Software ID/CFI Command Flowcharts © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A Software ID Entry Command Sequence Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH ...
Page 28
... Address: 2AAAH Load data: XX10H Address: 5555H Figure 21:Erase Command Sequence © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A Chip-Erase Sector-Erase Command Sequence Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH ...
Page 29
... A Microchip Technology Company Product Ordering Information SST © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A 200A - B3KE XXXX - XXXX 29 Data Sheet Environmental Attribute non-Pb Package Modifier leads or balls ...
Page 30
... Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combi- nations. © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A SST39LF200A-55-4C-B3KE SST39VF200A-70-4C-B3KE SST39VF200A-70-4I-B3KE SST39LF400A-55-4C-B3KE SST39VF400A-70-4C-B3KE ...
Page 31
... Maximum allowable mold flash is 0. the package ends, and 0.25 mm between leads. Figure 22:48-Lead Thin Small Outline Package (TSOP) 12mm x 20mm SST Package Code: EK © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A Pin # 1 Identifier 18.50 18.30 20.20 19.80 ...
Page 32
... Coplanarity: 0. Ball opening size is 0. 0.05 mm) Figure 23:48-Ball Thin-Profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm SST Package Code: B3K © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A TOP VIEW 8.00 0.10 6.00 0.10 1.10 0.10 SIDE VIEW 0.12 SEATING PLANE 0 ...
Page 33
... CORNER Note: Figure 24:48-Ball Very-Very-Thin-Profile, Fine-Pitch Ball Grid Array (WFBGA) 4mm x 6mm SST Package Code: M1Q © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A TOP VIEW 6.00 0.08 4.00 0.08 0.63 0.10 DETAIL ...
Page 34
... Coplanarity: 0. Ball opening size is 0. 0.05 mm) Figure 25:48-Ball Very-Very-Thin-Profile, Fine-Pitch Ball Grid Array (WFBGA) 4mm x 6mm SST Package Code: MAQ © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A TOP VIEW 6.00 0.08 4.00 0.08 0.73 max. 0.636 nom. ...
Page 35
... Note: 1. Complies with JEDEC Publication 95, MO-207, variant CZB-4, dimensions except bump height is much less. Figure 26: 48-Bump Extremely-Thin-Profile, Fine-Pitch Land Grid Array (XFLGA) 4mm x 6mm SST Package Code: C1Q © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A TOP VIEW 6.00 0.08 4.00 0.08 ...
Page 36
... Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A Description 2002 Data Book Added footnotes for MPF power usage and Typical conditions to Table 11 on page 15 Clarified the Test Conditions for Power Supply Current and Read parame- ...
Page 37
... SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of Sale. For sales office(s) location and information, please see www.microchip.com. © 2011 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A Silicon Storage Technology, Inc. A Microchip Technology Company www.microchip.com 37 Data Sheet ...