853S9252BKILF IDT, 853S9252BKILF Datasheet

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853S9252BKILF

Manufacturer Part Number
853S9252BKILF
Description
Clock Drivers & Distribution
Manufacturer
IDT
Datasheet

Specifications of 853S9252BKILF

Product Category
Clock Drivers & Distribution
Rohs
yes
Part # Aliases
ICS853S9252BKILF

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Part Number:
853S9252BKILF/W
Quantity:
1 770
Block Diagram
General Description
The ICS853S9252I is a 2.5V/3.3V ECL/LVPECL fanout buffer
designed for high-speed, low phase-noise wireless infrastructure
applications. The device fanouts a differential input signal to two
ECL/LVPECL outputs. Optimized for low additive phase-noise,
sub-100ps output rise and fall times, low output skew and
high-frequencies, the ICS853S9252I is an effective solution for
high-performance clock and data distribution applications, for
instance driving the reference clock inputs of ADC/DAC circuits.
Internal input termination, a bias voltage output (V
AC-coupling and small packaging (3.0mm x 3.0mm 16-lead VFQFN)
supports space-efficient board designs. The ICS853S9252I operates
from a full 2.5V or 3.3V power supply and supports the industrial
temperature range of -40°C to 85°C. The extended temperature
range also supports wireless infrastructure, tele-communication and
networking end equipment requirements.
ICS853S9252BKI REVISION A JULY 29, 2011
VREF
VTT
nIN
IN
50Ω
50Ω
Generator
VREF
Fanout Buffer
REF
Q0
nQ0
Q1
nQ1
) for
1
Features
1:2 differential clock/data fanout buffer
Two differential 2.5V/3.3V ECL/LVPECL clock output
Differential input accepts ECL/LVPECL, LVDS and CML levels
Additive phase jitter, RMS @ 122.88MHz: 45fs (typical)
Propagation delay: 175ps (maximum), V
Output rise/fall time: 135ps (maximum), V
Internal input signal termination
Supply voltage: 2.5V-5% to 3.3V+10%
Available in Lead-free (RoHS 6) package
-40°C to 85°C ambient operating temperature
Clock frequency: 3GHz (maximum)
Pin Assignment
3.0mm x 3.0mm x 0.925mm
nIN
IN
nc
nc
16 lead VFQFN
ICS853S9252I
package body
1
2
3
4
K Package
16 15 14 13
Top View
5 6
7
8
©2011 Integrated Device Technology, Inc.
12
11
10
9
CC
Q0
nQ0
Q1
nQ1
CC
= 3.3V
= 3.3V
DATA SHEET

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853S9252BKILF Summary of contents

Page 1

Fanout Buffer General Description The ICS853S9252I is a 2.5V/3.3V ECL/LVPECL fanout buffer designed for high-speed, low phase-noise wireless infrastructure applications. The device fanouts a differential input signal to two ECL/LVPECL outputs. Optimized for low additive phase-noise, sub-100ps output rise and ...

Page 2

ICS853S9252I Data Sheet Table 1. Pin Descriptions Number Name Type 1, 2 IN, nIN Input Unused Power Power nQ1, Q1 Output 11, 12 nQ0, Q0 ...

Page 3

ICS853S9252I Data Sheet Table 2B. DC Characteristics, V Symbol Parameter R Input Resistance IN V Input High Voltage IH V Input Low Voltage IL V Input Voltage Swing IN V Differential Input Voltage Swing DIFF_IN V Bias Voltage Reference REF ...

Page 4

ICS853S9252I Data Sheet AC Characteristics Table 3. AC Characteristics Symbol Parameter f Input Reference Frequency REF t Propagation Delay, NOTE 1 PD tsk(p) Output Pulse Skew tsk(o) Output Skew, NOTE 2, 3 tsk(pp) Part-to-Part Skew, NOTE 3, 4 ...

Page 5

ICS853S9252I Data Sheet Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase ...

Page 6

ICS853S9252I Data Sheet Parameter Measurement Information LVPECL V EE -1.63V to -0.375V Output Load AC Test Circuit Par t 1 nQx Qx Par t 2 nQy Qy tsk(pp) Part-to-Part Skew nIN IN nQ[0:1] Q[0:1] t PLH t ...

Page 7

... All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. ICS853S9252BKI REVISION A JULY 29, 2011 nQ[0:1] Q[0: Output Duty Cycle/Pulse Width/Period 7 2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER PERIOD t PW odc = x 100% t PERIOD © ...

Page 8

ICS853S9252I Data Sheet 3.3V Differential Input with Built-In 50 The IN /nIN with built-in 50Ω terminations accept LVDS, LVPECL, CML and other differential signals. Both differential signals must meet the V and V input requirements. Figures show ...

Page 9

ICS853S9252I Data Sheet 2.5V LVPECL Input with Built-In 50 The IN /nIN with built-in 50Ω terminations accept LVDS, LVPECL, CML and other differential signals. Both differential signals must meet the V and V input requirements. Figures show ...

Page 10

ICS853S9252I Data Sheet 2.5V Differential Input with Built- prevent oscillation and to reduce noise recommended to have pullup and pulldown connect to true and compliment of the unused input as shown in Figure 4A. 3.3V Differential ...

Page 11

ICS853S9252I Data Sheet Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that ...

Page 12

ICS853S9252I Data Sheet Termination for 2.5V LVPECL Outputs Figure 6A and Figure 6B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω – 2V. For V = 2.5V, the ...

Page 13

ICS853S9252I Data Sheet VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of ...

Page 14

ICS853S9252I Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the ICS853S9252I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853S9252I is the sum of the ...

Page 15

ICS853S9252I Data Sheet 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pairs. The LVPECL output driver circuit and termination are shown in Figure Figure 8. ...

Page 16

ICS853S9252I Data Sheet Reliability Information Table 5. θ vs. Air Flow Table for a 16 Lead VFQFN JA Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count forICS853S9252I is: 190 ICS853S9252BKI REVISION A JULY 29, ...

Page 17

ICS853S9252I Data Sheet 16 Lead VFQFN Package Outline and Package Dimensions ICS853S9252BKI REVISION A JULY 29, 2011 2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER 17 ©2011 Integrated Device Technology, Inc. ...

Page 18

... Marking 853S9252BKILF 252B 853S9252BKILFT 252B NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use ...

Page 19

... IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT ...

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