95V850AGLF IDT, 95V850AGLF Datasheet - Page 9

• Manufacturer Part Number: 95V850AGLF
• Description: Clock Drivers & Distribution
• Manufacturer: IDT

Specifications of 95V850AGLF

• Product Category: Clock Drivers & Distribution
• Rohs: yes
• Part # Aliases: ICS95V850AGLF

Recommended Layout for the ICS95V850
0458G—11/21/08
General Layout Precautions:
Use copper flooded ground on the top signal layer under the
clock buffer The area under U1 on the right is an example.
Flood over the ground vias.
1) Use power vias for power and ground. Vias 20 mil or
2) Make all power and ground traces are as wide as the via
3) VAA for pin 16 has a low pass RC filter to decouple the
4) Notice that ground vias are never shared.
5) When ever possible, VCC (net V2P5 in the schematic)
6) Differential mode clock output traces are routed:
7) Terminate differential CLK_IN and FB_IN traces after
Component Values:
Ref Desg.
C1,C4,C5,
C7,C11,C12
C2,C3,C8,
C9
C10
C6
R9,R12
R9
U1
larger in diameter have lower high frequency impedance.
Vias for signals may be minimum drill size.
pad for lower inductance.
digital and analog supplies. The 4.7uF capacitors may be
replaced with a single low ESR device with the same
total capacitance. VAA is routed on a outside signal
layer. Do not cut a power or ground plane and route in it.
pins have a decoupling capacitor. Power is always routed
from the plane connection via to the capacitor pad to the
VCC pin on the clock buffer. Moats or plane cuts are not
used to isolate power.
a.
b.
routing to buffer pads.
With a ground trace between the pairs. Trace is
grounded on both ends.
Without a ground trace, clock pairs are routed with a
separation of at least 5 times the thickness of the
dielectric. If the dielectric thickness is 4.5 mil, the
trace separation is at least 18 mils.
Value
.01uF
4.7uF
.22uF
2200pF
120
4.7
Description
CERAMIC MLC
CERAMIC MLC
CERAMIC MLC
CERAMIC MLC
ICS95V850
Package
0603
1206
0603
0603
0603
0603
TSSOP48
9
ICS95V850