8525BGLFT IDT, 8525BGLFT Datasheet

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8525BGLFT

Manufacturer Part Number
8525BGLFT
Description
Clock Drivers & Distribution
Manufacturer
IDT
Datasheet

Specifications of 8525BGLFT

Rohs
yes
Part # Aliases
ICS8525BGLFT
B
G
accept LVCMOS or LVTTL input levels and translate them
to LVHSTL levels. The clock enable is internally synchro-
nized to eliminate runt pulses on the outputs during asyn-
chronous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8525 ideal for those applications demanding
well defined performance and repeatability.
8525BG
HiPerClockS™
ICS
LOCK
ENERAL
CLK_SEL
CLK_EN
CLK0
CLK1
D
The ICS8525 is a low skew, high performance
1-to-4 LVCMOS-to-LVHSTL fanout buffer and a
member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8525 has two selectable clock inputs that
IAGRAM
D
ESCRIPTION
0
1
D
LE
Q
www.icst.com/products/hiperclocks.html
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
1
F
P
Four differential LVHSTL compatible outputs
Selectable LVCMOS / LVTTL clock inputs for redundant
and multiple frequency fanout applications
Maximum output frequency: 266MHz
Translates LVCMOS and LVTTL levels to LVHSTL levels
Output skew: 35ps (maximum)
Part-to-part skew: 150ps (maximum)
Propagation delay: 1.9ns (maximum)
3.3V core, 1.8V operating supply
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
Available in both standard and lead-free RoHS compliant
packages
EATURES
IN
LVCMOS-
A
SSIGNMENT
6.5mm x 4.4mm x 0.92mm Package Body
CLK_SEL
CLK_EN
CLK0
CLK1
TO
GND
V
nc
nc
nc
nc
DD
20-Lead TSSOP
-LVHSTL F
ICS8525
G Package
Top View
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
L
OW
Q0
nQ0
V
Q1
nQ1
Q2
nQ2
V
Q3
nQ3
DDO
DDO
ANOUT
S
ICS8525
KEW
REV. C AUGUST 1, 2007
, 1-
B
UFFER
TO
-4

Related parts for 8525BGLFT

8525BGLFT Summary of contents

Page 1

G D ENERAL ESCRIPTION The ICS8525 is a low skew, high performance ICS 1-to-4 LVCMOS-to-LVHSTL fanout buffer and a HiPerClockS™ member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8525 has two selectable clock inputs that ...

Page 2

ABLE IN ESCRIPTIONS ...

Page 3

T 3A ABLE ONTROL NPUT UNCTION ...

Page 4

BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, T STG T 4A ABLE OWER UPPLY HARACTERISTICS S y ...

Page 5

3.3V±5%, V ABLE HARACTERISTICS ...

Page 6

... Qx nQy Qy t sk( UTPUT KEW nQ0:nQ3 Q0: PERIOD t PW odc = t PERIOD UTPUT UTY YCLE ULSE IDTH ERIOD 8525BG LVCMOS EASUREMENT PART 1 nQx SCOPE Qx Qx PART 2 nQy nQx IRCUIT ART TO ART CLK0, CLK1 nQ0:nQ3 Q0: ROPAGATION ...

Page 7

R U ECOMMENDATIONS FOR NUSED I : NPUTS CLK I : NPUT For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection resistor can be tied ...

Page 8

This section provides information on power dissipation and junction temperature for the ICS8525. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8525 is the sum of the core power plus the power ...

Page 9

Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVHSTL output driver circuit and termination are shown in Figure 2. F IGURE To calculate worst case power dissipation into the load, ...

Page 10

ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second ...

Page 11

ACKAGE UTLINE UFFIX FOR T ABLE R EFERENCE 8525BG LVCMOS- TSSOP EAD ACKAGE IMENSIONS ...

Page 12

ABLE RDERING NFORMATION ...

Page 13

...

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