CSPUA877BVG IDT, CSPUA877BVG Datasheet

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... FUNCTIONAL BLOCK DIAGRAM 10KΩ - 100KΩ NOTE: The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and CLK. The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE c 2006 Integrated Device Technology, Inc. ...

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... IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PIN CONFIGURATION GND GND GND GND BALL VFBGA PACKAGE LAYOUT Y Y FBIN FBIN FBOUT DDQ GND OE V DDQ DDQ GND ...

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... IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER ABSOLUTE MAXIMUM RATINGS Symbol Rating Supply Voltage Range DDQ DD I (3) V Input Voltage Range O (3) V Voltage range applied to any output in the high or low state I Input clamp current IK (V < Output Clamp Current OK (V < > ...

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... IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PIN DESCRIPTION (VFBGA) Pin Name AGND AV DD CLK, CLK FBIN, FBIN FBOUT, FBOUT GND B2 - B5, C2, C5, H2, H5 D4, E2, E5, F2 DDQ A3, A4, B1, B6, C1, C6, K1, K2, K5, K6 [0:9] Y A1, A2, A5, A6, D1, D6, J1, J6, K3, K4 ...

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... IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial 0°C to +70°C A Symbol Parameter V Input Clamp Voltage (All Inputs (2) V Input LOW Voltage (OE, OS, CLK, CLK) IH (2) V Input HIGH Voltage (OE, OS, CLK, CLK) ...

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... SSC Clock Input Frequency Deviation CSPUA877 PLL designs should target the value below to minimize SSC-induced skew: PLL Loop Bandwidth (-3dB from unity gain) NOTES: 1. There are two different terminations that are used with the above AC tests. The output load shown in figure 1 is used to measure the input and output differential pair cross-voltage only. The output load shown in figure 2 is used to measure all other tests, including input and output slew rates. For consistency, use 50Ω ...

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... IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS V DDQ CSPUA877 GND V /2 DDQ Z = 60Ω 2.97" 60Ω 2.97" CSPUA877 V /2 DDQ Z = 60Ω 2.97" GND R = 120Ω 60Ω 2.97" GND Figure 1: Output Load Test Circuit 10Ω ...

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... IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS Yx, FBOUT Yx, FBOUT CLK CLK FBIN FBIN Yx Yx Yx, FBOUT Yx, FBOUT t t cycle n cycle n jit(cc) cycle n cycle n+1 Cycle-to-Cycle jitter t t (Ø) (Ø)n ∑ (Ø)n (Ø Static Phase Offset ...

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... IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS Yx, FBOUT Yx, FBOUT Yx, FBOUT Yx, FBOUT NOTE Average input frequency measured at CLK / CLK Yx, FBOUT Yx, FBOUT Yx, FBOUT Yx, FBOUT NOTE Average input frequency measured at CLK / CLK t cycle jit(per) = cycle Period jitter ...

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... IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS OE Y Time Delay Between Output Enable (OE) and Clock Output (Y, Y) CLK CLK FBIN FBIN SSC OFF SSC ON t (Ø)DYN 50% V DDQ t EN 50% V DDQ 50 (Ø) t (Ø)DYN ...

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... IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS 80% Clock Inputs and Outputs, OE 20% t SLR(I/O) BEAD VIA 1Ω 0603 CARD V DDQ GND VIA CARD NOTES: Place all decoupling capacitors as close to the CSPUA877 pins as possible. Use wide traces for A and AGND. ...

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... IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER APPLICATION INFORMATION CLK R = 120Ω CLK R = 120Ω 10pF Feedback path CLK R = 120Ω CLK R = 120Ω 10pF Feedback path ~2.5" CSPUA877 Z = 60Ω 60Ω 8 more FBIN FBIN Clock Structure 1 ~2.5" CSPUA877 Z = 60Ω ...

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... IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER ORDERING INFORMATION IDTCSPUA XXXXX XX Package Device Type CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 X Process Blank 0°C to +70°C (Commercial) BVG Very Fine Pitch Ball Grid Array, Green 1.8V PLL Differential 1:10 SDRAM Clock Driver ...