8344AY-01LFT IDT, 8344AY-01LFT Datasheet

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8344AY-01LFT

Manufacturer Part Number
8344AY-01LFT
Description
Clock Drivers & Distribution
Manufacturer
IDT
Datasheet

Specifications of 8344AY-01LFT

Rohs
yes
Part # Aliases
ICS8344AY-01LFT
B
8344BY
G
The ICS8344 is a low voltage, low skew, 1-to-24 Differential-
to-LVCMOS Fanout Buffer. The ICS8344 is designed to trans-
late any differential signal levels to LVCMOS levels. The low
impedance LVCMOS outputs are designed to drive 50Ω se-
ries or parallel terminated transmission lines. The effective
fanout can be increased to 48 by utilizing the ability of the
outputs to drive two series terminated lines. Redundant clock
applications can make use of the dual clock input. The dual
clock inputs also facilitate board level testing. ICS8344 is
characterized at full 3.3V, full 2.5V and mixed 3.3V input and
2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics
make the ICS8344 ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
LOCK
ENERAL
CLK_SEL
nCLK1
nCLK0
CLK0
CLK1
OE1
OE2
OE3
D
IAGRAM
D
ESCRIPTION
0
1
Q0:Q7
O8:Q15
O16:Q23
1
D
F
• Twenty-four LVCMOS outputs, 7Ω typical output impedance
• Selectable differential clock input pairs for redundant
• CLKx, nCLKx pairs can accept the following differential
• Maximum output frequency: 167MHz
• Translates any differential input signal (LVPECL, LVHSTL,
• Translates any single-ended input signal to LVCMOS
• Multiple output enable pins for disabling unused outputs
• Output skew: 275ps (maximum)
• Part-to-part skew: 600ps (maximum)
• Bank skew: 150ps (maximum)
• Propagation Delay: 4.3ns (maximum)
• 3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes
• 0°C to 70°C ambient operating temperature
• Available in standard (RoHS 5) and lead-free (RoHS 6)
P
IFFERENTIAL
clock applications
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
LVDS) to LVCMOS without external bias networks
with resistor bias on nCLK input
in reduced fanout applications
packages
EATURES
IN
A
GND
GND
V
V
Q16
Q17
Q18
Q19
Q20
Q21
Q22
Q23
DDO
DDO
SSIGNMENT
7mm x 7mm x 1.4mm package body
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
-
TO
-LVCMOS F
48-Lead LQFP
ICS8344
Y Package
Top View
L
OW
S
ANOUT
KEW
ICS8344
REV. A JANUARY 5, 2011
36
35
34
33
32
31
30
29
28
27
26
25
, 1-
Q7
Q6
V
GND
Q5
Q4
Q3
Q2
V
GND
Q1
Q0
B
DDO
DDO
TO
UFFER
-24

Related parts for 8344AY-01LFT

8344AY-01LFT Summary of contents

Page 1

G D ENERAL ESCRIPTION The ICS8344 is a low voltage, low skew, 1-to-24 Differential- to-LVCMOS Fanout Buffer. The ICS8344 is designed to trans- late any differential signal levels to LVCMOS levels. The low impedance LVCMOS outputs are designed to drive ...

Page 2

ABLE IN ESCRIPTIONS ...

Page 3

T 3A ABLE UTPUT NABLE UNCTION ...

Page 4

BSOLUTE AXIMUM ATINGS Supply Voltage, V DDx Inputs Outputs Package Thermal Impedance, θ JA Storage Temperature, T STG Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. ...

Page 5

T 5A ABLE HARACTERISTICS ...

Page 6

T 4D ABLE OWER UPPLY HARACTERISTICS ...

Page 7

T 5B ABLE HARACTERISTICS ...

Page 8

T 4G ABLE OWER UPPLY HARACTERISTICS ...

Page 9

T 5C ABLE HARACTERISTICS ...

Page 10

P ARAMETER 1.65V±5% V DD, V DDO LVCMOS GND -1.65V±5% 2.05V±5% 1.25V± DDO LVCMOS GND -1.25V±5% 8344BY D IFFERENTIAL M I EASUREMENT NFORMATION Qx 3. UTPUT OAD EST IRCUIT 3.3V/2. ...

Page 11

DDO LVCMOS GND -1.25V± nCLK0, nCLK1 CLK0, CLK1 GND Qx Qy 8344BY D IFFERENTIAL 2. UTPUT OAD EST IRCUIT V Cross Points IFFERENTIAL NPUT EVEL V ...

Page 12

PART 1 Qx PART 2 Qy 30% Clock Inputs and Outputs nCLK0, nCLK1 CLK0, CLK1 Q0:Q23 Q0:Q23 8344BY D IFFERENTIAL V DDO 2 V DDO 2 tsk(pp ART TO ART KEW 70 ...

Page 13

W D IRING THE Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias circuit should be located ...

Page 14

ABLE VS IR LOW ABLE JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: For 48-pin LQFP T C RANSISTOR OUNT The transistor count for ICS8344 is: 1449 ...

Page 15

ACKAGE UTLINE UFFIX ABLE θ θ θ θ θ Reference Document: JEDEC Publication ...

Page 16

ABLE RDERING NFORMATION ...

Page 17

8344BY D IFFERENTIAL ...

Page 18

... San Jose, CA 95138 © 2011 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners ...

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