83940DKILF IDT, 83940DKILF Datasheet

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83940DKILF

Manufacturer Part Number
83940DKILF
Description
Clock Drivers & Distribution
Manufacturer
IDT
Datasheet

Specifications of 83940DKILF

Product Category
Clock Drivers & Distribution
Rohs
yes
Part # Aliases
ICS83940DKILF
The ICS83940DI is a low skew, 1-to-18 LVPECL- to-LVCMOS/LVTTL
The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The
The ICS83940DI is characterized at full 3.3V and 2.5V or mixed 3.3V
General Description
Fanout Buffer. The ICS83940DI has two selectable clock inputs. The
PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels.
low impedance LVCMOS/LVTTL outputs are designed to drive 50
series or parallel terminated transmission lines.
core, 2.5V output operating supply modes. Guaranteed output and
part-to-part skew characteristics make the ICS83940DI ideal for
those clock distribution applications demanding well defined
performance and repeatability.
Block Diagram
Pin Assignments
ICS83940DYI REVISION C
LVCMOS_CLK
LVCMOS_CLK
CLK_SEL
nPCLK
CLK_SEL
PCLK
nPCLK
PCLK
5mm x 5mm x 0.925mm package body
V
GND
GND
V
DDO
DD
Pullup/Pulldown
Pulldown
Pulldown
Pulldown
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
9
10 11 12 13 14 15 16
ICS83940DI
32 Lead VFQFN
MARCH 20, 2013
Low Skew, 1-to18
LVPECL-to-LVCMOS/LVTTL Fanout Buffer
K Package
Top View
0
1
24
23
22
21
20
19
18
17
Q9
Q10
Q6
Q7
Q8
V
Q11
GND
DD
18
Q0:Q17
1
Features
Eighteen LVCMOS/LVTTL outputs
Selectable LVCMOS_CLK or LVPECL clock inputs
PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, CML, SSTL
LVCMOS_CLK supports the following input types: LVCMOS or
LVTTL
Maximum output frequency: 250MHz
Output skew: 150ps (maximum)
Part-to-part skew: 750ps (maximum)
Operating supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
LVCMOS_CLK
CLK_SEL
nPCLK
PCLK
GND
GND
V
7mm x 7mm x 1.4mm package body
V
DDO
DD
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
ICS83940DI
32-Lead LQFP
Y Package
Top View
©2013 Integrated Device Technology, Inc.
ICS83940DI
24
23
22
21
20
19
18
17
DATA SHEET
Q6
Q7
Q8
V
Q9
Q10
Q11
GND
DD

Related parts for 83940DKILF

83940DKILF Summary of contents

Page 1

Low Skew, 1-to18 LVPECL-to-LVCMOS/LVTTL Fanout Buffer General Description The ICS83940DI is a low skew, 1-to-18 LVPECL- to-LVCMOS/LVTTL Fanout Buffer. The ICS83940DI has two selectable clock inputs. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The LVCMOS_CLK ...

Page 2

ICS83940DI Data Sheet Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name 1, 2, 12, 17, 25 GND 3 LVCMOS_CLK 4 CLK_SEL 5 PCLK 6 nPCLK 16 DDO 9, 10, 11, Q17, ...

Page 3

ICS83940DI Data Sheet Function Tables Table 3A. Clock Select Function Table Control Input CLK_SEL PCLK, nPCLK 0 Selected 1 De-selected Table 3B. Clock Input Function Table Inputs CLK_SEL LVCMOS_CLK 0 – 0 – 0 – 0 – 0 – Biased; ...

Page 4

ICS83940DI Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those ...

Page 5

ICS83940DI Data Sheet Table 4C. DC Characteristics Symbol Parameter V Input High Voltage IH V Input Low Voltage IL I Input Current IN V Output High Voltage OH V Output Low Voltage OL Peak-to-Peak Input Voltage ...

Page 6

ICS83940DI Data Sheet AC Electrical Characteristics Table 5A. AC Characteristics Symbol Parameter f Output Frequency MAX PCLK, nPCLK; NOTE 1, 5 Propagation Delay LVCMOS_CLK; NOTE PLH PCLK, nPCLK; NOTE 1, 5 Propagation Delay LVCMOS_CLK; NOTE ...

Page 7

ICS83940DI Data Sheet Table 5B. AC Characteristics Symbol Parameter f Output Frequency MAX PCLK, nPCLK; NOTE 1, 5 Propagation Delay LVCMOS_CLK; NOTE PLH PCLK, nPCLK; NOTE 1, 5 Propagation Delay LVCMOS_CLK; NOTE 2, 5 PCLK, ...

Page 8

ICS83940DI Data Sheet Table 5C. AC Characteristics Symbol Parameter f Output Frequency MAX PCLK, nPCLK; NOTE 1, 5 Propagation Delay LVCMOS_CLK; NOTE PLH PCLK, nPCLK; NOTE 1, 5 Propagation Delay LVCMOS_CLK; NOTE 2, 5 PCLK, ...

Page 9

ICS83940DI Data Sheet Parameter Measurement Information 1.65V±5% V DD, V DDO GND -1.65V±5% 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit 2.05V±5% 1.25V± DDO GND -1.25V±5% 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit Part 1 V ...

Page 10

... PCLK V DD LVCMOS_CLK 2 V DDO Q0:Q17 Propagation Delay ICS83940DYI REVISION C MARCH 20, 2013 LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER 2.4V 0.5V Q0:Q17 t F 2.5V Output Rise/Fall Time Q0:Q17 Output Duty Cycle/Pulse Width/Period 10 1.8V 1.8V 0. DDO PERIOD 100% odc = t PERIOD ©2013 Integrated Device Technology, Inc. ...

Page 11

ICS83940DI Data Sheet Application Information Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage V the bias resistors R1 and R2. The bypass ...

Page 12

ICS83940DI Data Sheet LVPECL Clock Input Interface The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both differential signals must meet the V V input requirements. Figures show interface examples CMR for the PCLK/nPCLK input ...

Page 13

ICS83940DI Data Sheet VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of ...

Page 14

ICS83940DI Data Sheet Reliability Information Table 6A.  vs. Air Flow Table for a 32 Lead LQFP JA Linear Feet per Minute Multi-Layer PCB, JEDEC Standard Test Boards Table 6B.  vs. Air Flow Table for a 32 Lead VFQFN ...

Page 15

ICS83940DI Data Sheet Package Outline and Package Dimensions Package Outline - Y Suffix for 32 Lead LQFP Table 7A. Package Dimensions for 32 Lead LQFP JEDEC Variation: ABC - HD All Dimensions in Millimeters Symbol Minimum Nominal ...

Page 16

ICS83940DI Data Sheet Package Outline and Package Dimensions Package Outline - K Suffix for 32 Lead VFQFN S eating Plan e Ind ex Area View D Chamfer 4x 0.6 x 0.6 max OPTIONAL Bottom View w/Type A ...

Page 17

... Ordering Information Table 8. Ordering Information Part/Order Number Marking 83940DYILF ICS83940DYIL 83940DYILFT ICS83940DYIL 83940DKILF ICS83940DIL 83940DKILFT ICS83940DIL ICS83940DYI REVISION C MARCH 20, 2013 LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Package Shipping Packaging “Lead-Free” 32 Lead LQFP “Lead-Free” 32 Lead LQFP “Lead-Free” 32 Lead VFQFN “ ...

Page 18

ICS83940DI Data Sheet Revision History Sheet Rev Table Page T6B 14 B T7B ...

Page 19

... IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi- cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. ...

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