CSPU877BVG8 IDT, CSPU877BVG8 Datasheet
CSPU877BVG8
Specifications of CSPU877BVG8
Related parts for CSPU877BVG8
CSPU877BVG8 Summary of contents
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... FUNCTIONAL BLOCK DIAGRAM 10KΩ - 100KΩ NOTE: The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and CLK. The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE c 2006 Integrated Device Technology, Inc. ...
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... IDTCSPU877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PIN CONFIGURATION GND GND GND GND BALL VFBGA PACKAGE LAYOUT Y Y FBIN FBIN FBOUT GND OS DDQ DDQ DDQ ...
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... IDTCSPU877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PIN CONFIGURATION 1 V DDQ CLK CLK 5 GND V 6 DDQ AGND DDQ 10 GND VFQFPN TOP VIEW RECOMMENDED OPERATING CONDITIONS Symbol DD (1) AV Supply Voltage V I/O Supply Voltage DDQ T Operating Free-Air Temperature A NOTE: 1 ...
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... IDTCSPU877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PIN DESCRIPTION (VFBGA) Pin Name AGND AV DD CLK, CLK FBIN, FBIN FBOUT, FBOUT GND B2 - B5, C2, C5, H2, H5 D4, E2, E5, F2 DDQ A3, A4, B1, B6, C1, C6, K1, K2, K5, K6 [0:9] Y A1, A2, A5, A6, D1, D6, J1, J6, K3, K4 ...
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... IDTCSPU877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER FUNCTION TABLE (1,2) INPUTS GND H X GND H X GND L H GND L L 1.8V (nom 1.8V (nom 1.8V (nom 1.8V (nom 1.8V (nom NOTES HIGH Voltage Level L = LOW Voltage Level X = Don't Care 2. L(z) means the outputs are disabled to a LOW state, meeting the I 3 ...
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... Modulation Frequency SSC Clock Input Frequency Deviation f PLL Loop Bandwidth 3dB NOTES: 1. There are two different terminations that are used with the above AC tests. The output load shown in figure 1 is used to measure the input and output differential pair cross-voltage only. The output load shown in figure 2 is used to measure all other tests, including input and output slew rates. For consistency, use 50Ω equal length cables with SMA connectors on the test board ...
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... IDTCSPU877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS V DDQ CSPU877 GND V /2 DDQ Z = 60Ω 2.97" 60Ω 2.97" CSPU877 V /2 DDQ Z = 60Ω 2.97" GND R = 120Ω 60Ω 2.97" GND Figure 1: Output Load Test Circuit 10Ω ...
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... IDTCSPU877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS Yx, FBOUT Yx, FBOUT CLK CLK FBIN FBIN Yx Yx Yx, FBOUT Yx, FBOUT t t cycle n cycle n jit(cc) cycle n cycle n+1 Cycle-to-Cycle jitter t t (Ø) (Ø)n ∑ (Ø)n (Ø Static Phase Offset ...
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... IDTCSPU877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS Yx, FBOUT Yx, FBOUT Yx, FBOUT Yx, FBOUT NOTE Average input frequency measured at CLK / CLK Yx, FBOUT Yx, FBOUT Yx, FBOUT Yx, FBOUT NOTE Average input frequency measured at CLK / CLK t cycle jit(per) = cycle Period jitter ...
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... IDTCSPU877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS OE Y Time Delay Between Output Enable (OE) and Clock Output (Y, Y) CLK CLK FBIN FBIN SSC OFF SSC ON t (Ø)DYN 50% V DDQ t EN 50% V DDQ 50 (Ø) t (Ø)DYN ...
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... IDTCSPU877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS 80% Clock Inputs and Outputs SLR(I/O) BEAD VIA 1Ω 0603 CARD V DDQ 4.7uF 1206 GND VIA CARD NOTES: Place all decoupling capacitors as close to the CSPU877 pins as possible. Use wide traces for A and AGND ...
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... IDTCSPU877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER APPLICATION INFORMATION CLK R = 120Ω CLK FBIN R = 120Ω 10pF FBIN Feedback path CLK R = 120Ω CLK C = 10pF R = 120Ω Feedback path ~2.5" CSPU877 Z = 60Ω 60Ω 8 more Clock Structure 1 ~2.5" CSPU877 Z = 60Ω ...
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... Very Fine Pitch Ball Grid Array BVG Very Fine Pitch Ball Grid Array. Green NL Thermally Enhanced Plastic Very Fine Pitch Quad Flat Pack No Lead Package 1.8V PLL Differential 1:10 SDRAM Clock Driver 877 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 13 COMMERCIAL TEMPERATURE RANGE for Tech Support: logichelp@idt.com ...