8534BMI-13LF IDT, 8534BMI-13LF Datasheet - Page 13

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8534BMI-13LF

Manufacturer Part Number
8534BMI-13LF
Description
Clock Drivers & Distribution
Manufacturer
IDT
Datasheet

Specifications of 8534BMI-13LF

Product Category
Clock Drivers & Distribution
Rohs
yes
Part # Aliases
ICS8534BMI-13LF
ICS8534-01 Data Sheet
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
Figure 5A. 3.3V LVPECL Output Termination
ICS8534AY-01 REVISION B MARCH 28, 2011
RTT =
((V
3.3V
OH
LVPECL
+ V
OL
) / (V
1
CC
Z
Z
– 2)) – 2
o
o
= 50Ω
= 50Ω
* Z
R1
50Ω
o
RTT
R2
50Ω
V
+
_
CC
3.3V
- 2V
Input
13
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 5B. 3.3V LVPECL Output Termination
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
3.3V
LVPECL
Z
Z
o
o
= 50Ω
= 50Ω
R3
125Ω
©2011 Integrated Device Technology, Inc.
R1
84Ω
3.3V
R4
125Ω
R2
84Ω
+
_
3.3V
Input

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