CSP2510DPGG IDT, CSP2510DPGG Datasheet

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CSP2510DPGG

Manufacturer Part Number
CSP2510DPGG
Description
Clock Drivers & Distribution 10 + 1 Outputs 3.3V PLL Clk Driver PC133
Manufacturer
IDT
Type
PLL Clock Driversr
Datasheet

Specifications of CSP2510DPGG

Rohs
yes
Multiply / Divide Factor
1
Max Output Freq
175 MHz
Supply Voltage - Max
3.6 V
Supply Voltage - Min
3 V
Maximum Operating Temperature
+ 85 C
Package / Case
TSSOP-24
Input Type
Clock
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Current
10 uA
Part # Aliases
IDTCSP2510DPGG
FEATURES:
• Phase-Lock Loop Clock Distribution for Synchronous DRAM
• Distributes one clock input to one bank of ten outputs
• Output enable bank control
• External feedback (FBIN) pin is used to synchronize the
• No external RC network required for PLL loop stability
• Operates at 3.3V V
• tpd Phase Error at 166MHz: < ±150ps
• Jitter (peak-to-peak) at 166MHz: < ±75ps @ 166MHz
• Spread Spectrum Compatible
• Operating frequency 50MHz to 175MHz
• Available in 24-Pin TSSOP package
APPLICATIONS:
• SDRAM Modules
• PC Motherboards
• Workstations
0º º º º º C TO 85º º º º º C TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
IDTCSP2510D
3.3V PHASE-LOCK LOOP CLOCK DRIVER
c
Applications
outputs to the clock input signal
2001 Integrated Device Technology, Inc.
FUNCTIONAL BLOCK DIAGRAM
DD
AV
FBIN
CLK
DD
G
24
13
23
11
3.3V PHASE-LOCK LOOP
CLOCK DRIVER
ZERO DELAY BUFFER
PLL
1
DESCRIPTION:
loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency
and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CSP2510D
operates at 3.3V.
Output signal duty cycles are adjusted to 50 percent, independent of the duty
cycle at CLK. The outputs can be enabled or disabled via the control G input.
When the G input is high, the outputs switch in phase and frequency with
CLK; when the G input is low, the outputs are disabled to the logic-low state.
external RC networks. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.
stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required, following power up and
application of a fixed-frequency, fixed-phase signal at CLK, as well as
following any changes to the PLL reference or feedback signals. The PLL
can be bypassed for the test purposes by strapping AV
is also available (on special order) in Industrial temperature range (-40°C
to +85°C). See ordering information for details.
The CSP2510D is a high performance, low-skew, low-jitter, phase-lock
One bank of ten outputs provide low-skew, low-jitter copies of CLK.
Unlike many products containing PLLs, the CSP2510D does not require
Because it is based on PLL circuitry, the CSP2510D requires a
The CSP2510D is specified for operation from 0°C to +85°C. This device
12
16
17
20
21
15
3
4
5
8
9
Y0
Y1
Y2
Y3
Y4
FBOUT
Y5
Y6
Y7
Y8
Y9
0
°
C TO 85
°
C TEMPERATURE RANGE
IDTCSP2510D
OCTOBER 2001
DD
to ground.
DSC-5874/3

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CSP2510DPGG Summary of contents

Page 1

... FUNCTIONAL BLOCK DIAGRAM G CLK FBIN AV DD The IDT logo is a registered trademark of Integrated Device Technology, Inc. 0º º º º º 85º º º º º C TEMPERATURE RANGE c 2001 Integrated Device Technology, Inc. 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER ...

Page 2

... IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER PIN CONFIGURATION AGND GND 7 GND FBOUT 12 TSSOP TOP VIEW RECOMMENDED OPERATING CONDITIONS Symbol Power Supply Voltage Operating Free-Air Temperature A ABSOLUTE MAXIMUM RATINGS Symbol (1) ...

Page 3

... IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER PIN DESCRIPTION Terminal Name No. Type CLK 24 I Clock input. CLK provides the clock signal to be distributed by the CSP2510D clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock ...

Page 4

... IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER DC ELECTRICAL CHARACTERISTICS OVER OPERATING FREE-AIR TEMPERA- TURE RANGE (1) Symbol Description V Input Clamp Voltage IK V Input HIGH Level IH V Input LOW Level IL V HIGH Level Output Voltage OH V LOW Level Output Voltage OL I Input Current I I Supply Current DD Δ ...

Page 5

... IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER SWITCHING CHARACTERISTICS OVER OPERATING RANGE OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C Parameter (2) From (Input) t error 100MHz < CLK↑ < 166MHz PHASE (3) t error – jitter CLK↑ = 166MHz PHASE t (4) Any Y (166MHz) SK(o) Jitter (cycle-cycle) CLK = 166MHz (peak-to-peak) ...

Page 6

... IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER PARAMETER MEASUREMENT INFORMATION From Output Under Test C = 30pF L Y CLK C = 30pF L CSP2510D F BOUT F BIN C F PCB TRACE NOTES: 1. All inputs pulses are supplied by generators having the following characteristics includes probe and jig capacitance The outputs are measured one at a time with one transition per measurement. ...

Page 7

... IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER TYPICAL CHARACTERISTICS 200 150 100 -50 -100 -150 -200 Phase Error vs Clock Frequency AV and 25C 66 100 133 Clock Frequency (MHz) Analog Supply Current vs Clock Frequency AV and 25C ...

Page 8

... IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER TYPICAL CHARACTERISTICS (CONT 140 120 100 Cycle-to-Cycle 0 50 Output Duty Cycle vs Clock Frequency AV and 25C 66 100 133 Clock Frequency (MHz) Jitter vs Clock Frequency AV and V = 3.3V DD ...

Page 9

... San Jose, CA 95138 X Process Blank I PG 2510D for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 9 ° ° TEMPERATURE RANGE 0°C to +85°C (Standard) -40°C to +85°C (Industrial) Thin Shrink Small Outline Package Phase-Lock Loop Clock Driver for Tech Support: logichelp@idt.com ...

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