1337GDCGI IDT, 1337GDCGI Datasheet - Page 4
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1337GDCGI
Manufacturer Part Number
1337GDCGI
Description
Real Time Clock Real Time Clock
Manufacturer
IDT
Datasheet
1.1337GDCGI.pdf
(27 pages)
Specifications of 1337GDCGI
Rohs
yes
Function
Clock, Calendar, Alarm
Rtc Bus Interface
I2C
Date Format
YY-MM-DD-dd
Time Format
HH
Supply Voltage - Max
5.5 V
Supply Voltage - Min
1.8 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Package / Case
SOIC-8
Battery Backup Switching
No
Part # Aliases
IDT1337GDCGI
Typical Operating Circuit
Detailed Description
Communications to and from the IDT1337G occur serially
over an I
on the serial bus. Access is obtained by implementing a
START condition and providing a device identification code,
followed by data. Subsequent registers can be accessed
sequentially until a STOP condition is executed. The device
is fully accessible through the I
is between 5.5 V and 1.8 V. I
when VCC is below 1.8 V. The IDT1337G maintains the time
and date when VCC is as low as 1.3 V.
The following sections discuss in detail the Oscillator block,
Clock/Calendar Register Block and Serial I
Oscillator Block
Selection of the right crystal, correct load capacitance and
careful PCB layout are important for a stable crystal
oscillator. Due to the optimization for the lowest possible
current in the design for these oscillators, losses caused by
parasitic currents can have a significant impact on the
overall oscillator performance. Extra care needs to be taken
to maintain a certain quality and cleanliness of the PCB.
Crystal Selection
The key parameters when selecting a 32 kHz crystal to work
with IDT1337G RTC are:
•
•
•
IDT® REAL-TIME CLOCK WITH I
IDT1337G
REA LTIME CLOCK WITH SERIAL INTERFACE
Recommended Load Capacitance
Crystal Effective Series Resistance (ESR)
Frequency Tolerance
2
C bus. The IDT1337G operates as a slave device
CPU
V
CC
2
C SERIAL INTERFACE
2
C operation is not guaranteed
2
C interface whenever VCC
2k
2k
2
V
C block.
CC
SDA
SCL
CRYSTAL
X1
IDT1337G
X2
GND
4
Effective Load Capacitance
Please see diagram below for effective load capacitance
calculation. The effective load capacitance (CL) should
match the recommended load capacitance of the crystal in
order for the crystal to oscillate at its specified parallel
resonant frequency with 0ppm frequency error.
In the above figure, X1 and X2 are the crystal pins of our
device. Cin1 and Cin2 are the internal capacitors which
include the X1 and X2 pin capacitance. Cex1 and Cex2 are
the external capacitors that are needed to tune the crystal
frequency. Ct1 and Ct2 are the PCB trace capacitances
between the crystal and the device pins. CS is the shunt
capacitance of the crystal (as specified in the crystal
manufacturer's datasheet or measured using a network
analyzer).
SQW/INTB
V
V
CC
CC
INTA
10k
10k
IDT1337G
REV L 102412
RTC