DS1004C-303 Maxim Integrated, DS1004C-303 Datasheet
DS1004C-303
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DS1004C-303 Summary of contents
Page 1
FEATURES All-silicon timing circuit Five delayed clock phases per input Precise tap-to-tap nominal delay tolerances of ±0.75 and ±1 ns Input-to-tap 1 delay Nominal Delay tolerances of ±1.5 ns Leading and trailing edge precision preserves the ...
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PART NUMBER TOLERANCE TABLE Table 1 INPUT-TO-TAP TOLERANCE PART NOMINAL NUMBER DS1004M-2 1.5 ns DS1004M-3 1.5 ns DS1004M-4 1.5 ns DS1004M-5 1.5 ns DS1004Z-2 1.5 ns DS1004Z-3 1.5 ns DS1004Z-4 1.5 ns DS1004Z-5 1.5 ns NOTES: 1. Nominal conditions are ...
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DS1004 TEST CIRCUIT Figure 1 TEST SETUP DESCRIPTION Figure 1 illustrates the hardware configuration used for measuring the timing parameters of the DS1004. The input waveform is produced by a precision pulse generator under software control. Time delays are measured ...
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ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature Short Circuit Output Current * This is a stress rating only and functional operation of the device at these or any other conditions above ...
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NOTES: 1. All voltages are referenced to ground =5V and 25 C. Delay accuracy on both the rising and falling edges within tolerances given in CC Table 1. 3. Pulse width and duty cycle specifications may be exceeded, ...
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TERMINOLOGY Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the ...