DS1602S+TRL Maxim Integrated, DS1602S+TRL Datasheet - Page 2

• Manufacturer Part Number: DS1602S+TRL
• Description: Real Time Clock
• Manufacturer: Maxim Integrated
• Series: DS1602r

Specifications of DS1602S+TRL

• Rohs: yes
• Function: Clock, Calendar, Elapsed Time Counter
• Rtc Bus Interface: Serial
• Time Format: Binary
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Part # Aliases: 90-1602S+TRL

OPERATION
The main elements of the DS1602 are shown in Figure 1. As shown, communications to and from the
elapsed time counter occur over a 3-wire serial port. The port is activated by driving
With
select, register clear, and oscillator trim information. Each bit is serially input on the rising edge of the
clock input. After the first eight clock cycles have loaded the protocol register with a valid protocol,
additional clocks will output data for a read or input data for a write. V
DS1602. If V
conserve battery capacity. For battery only operations, the V
must be connected to the battery. This will keep the DS1602 out of battery backup mode. Battery
powered operation down to 2.5V is possible with reduced speed performance on the serial port. The 32-
bit continuous counter always runs provided that a valid supply is present and the oscillator is enabled.
The 32-bit V
PROTOCOL REGISTER
The protocol bit definition is shown in Figure 2. Valid protocols and the resulting actions are shown in
Table 1. Each data transfer to the protocol register designates what action is to occur. As defined, the
MSB (bit 7 which is designated ACC) selects the 32-bit continuous counter for access. If ACC is a logical
1 the continuous counter is selected and the 32 clock cycles that follow the protocol will either read or
write this counter. If the counter is being read, the contents will be latched into a different register at the
end of protocol and the latched contents will be read out on the next 32 clock cycles. This avoids reading
garbled data if the counter is clocked by the oscillator during a read. Similarly, if the counter is to be
written, the data is buffered in a register and all 32 bits are jammed into the counter simultaneously on the
rising edge of the 32
counter for access. If AVC is a logical 1 this counter is selected and the 32 clock cycles that follow will
either read or write this counter. If both bit 7 and bit 6 are written to a logic high, all clock cycles beyond
the protocol are ignored and bits 5, 4, and 3 are loaded into the oscillator trim register. A value of binary 3
(011) will give a clock accuracy of ±120 seconds per month at +25 C. Increasing the binary number
towards 7 will cause the real- time clock to run faster. Conversely, lowering the binary number towards 0
will cause the clock to run slower. Binary 000 will stop the oscillator completely. This feature can be used
to conserve battery life during storage. In this mode the I
applications where oscillator trimming is not practical or not needed, a default setting of 011 is
recommended. Bit 2 of protocol (designated CCC) is used to clear the continuous counter. When set to
logic 1, the continuous counter will reset to 0 when
is used to clear the V
1. Bit 0 of the protocol (designated RD) determines whether the 32 clocks to follow will write a counter
or read a counter. When RD is set to a logical 0 a write action will follow when RD is set to a logical 1 a
read action will follow. When sending the protocol, 8 bits should always be sent. Sending less than 8 bits
can produce erroneous results. If clearing the counters or trimming the oscillator, the data transfer can be
terminated after the 8-bit protocol is sent. However, when reading or writing the counters, 32 clock cycles
should always follow the protocol.
RESET AND CLOCK CONTROL
All data transfers are initiated by driving the
Second, the
RST
RST
turns on the serial port logic, which allows access to the protocol register for the protocol data entry.
is taken low. Both counters can be reset simultaneously by setting CCC and CVC both to a logical
RST
at high level, 8 bits are loaded into the protocol shift register providing read/write, register
CC
RST
CC
active counter is gated by V
< V
signal provides a method of terminating the protocol transfer or the 32-bit counter
nd
TP
CC
clock. The next bit (bit 6 which is designated AVC) selects the 32-bit V
, the DS1602 goes into a battery backup mode which disables the serial port to
active counter. When set to logical 1, the V
CC
and the internal 1Hz signal.
RST
2 of 8
RST
input high. The
is taken low. Bit 1 of protocol (designated CVC)
BAT
BAT
current is reduced to 100nA maximum. In
pin must be grounded and the V
CC
RST
active counter will reset to 0 when
CC
input has two functions. First,
must be present to access the
RST
to a high state.
CC
DS1602
CC
active
pin