MAX6909EO33 Maxim Integrated, MAX6909EO33 Datasheet - Page 22

• Manufacturer Part Number: MAX6909EO33
• Description: Real Time Clock
• Manufacturer: Maxim Integrated
• Series: MAX6909, MAX6910r

Specifications of MAX6909EO33

• Function: Clock, Calendar, Watchdog Timekeeper, NV SRAM Control
• Rtc Bus Interface: Serial
• Time Format: HH
• Rtc Memory Size: 31 B
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-20

There is a way to help the watchdog-timer monitor soft-
ware execution more closely, which involves setting
and resetting the watchdog input at different points in
the program rather than “pulsing” the watchdog input
high-low-high or low-high-low. This technique avoids a
“stuck” loop, in which the watchdog timer continues to
be reset within the loop, keeping the watchdog from
timing out. Figure 10 shows an example of how the I/O
driving the watchdog input is set high at the beginning
of the program, set low at the beginning of every sub-
routine or loop, then set high again when the program
returns to the beginning. If the program should “hang”
in any subroutine, the problem would quickly be cor-
rected since the I/O is continually set low and the
watchdog timer is allowed to time out, causing a reset
to be issued.
Internal gating of chip-enable (CE) signals prevents erro-
neous data from corrupting CMOS RAM in the event of an
undervoltage condition. The MAX6909/MAX6910
use a transmission gate from CE IN to CE OUT. During
normal operation (reset not asserted), the transmission
gate is enabled and passes all CE transitions. When reset
is asserted, this path becomes disabled, preventing erro-
neous data from corrupting the CMOS RAM. The short
CE propagation delay from CE IN to CE OUT enables the
MAX6909/MAX6910 to be used with most microproces-
sors. If CE IN is low when reset asserts, CE OUT remains
low for typically t
write cycle. Figure 11 shows the chip-enable transmission
gate.
I
Supervisor and NV RAM Controller
Figure 10. Watchdog Flow Diagram
22
2
C-Compatible Real-Time Clocks with µP
______________________________________________________________________________________
RCE
Watchdog Software Considerations
to permit completion of the current
Chip-Enable Signal Gating
SUBROUTINE OR
PROGRAM LOOP
SET WDI LOW
PROGRAM
SET WDI
RETURN
START
CODE
HIGH
The CE transmission gate is disabled and CE IN is high
impedance (disabled mode) while reset is asserted.
During a power-down sequence when V
the reset threshold, the CE transmission gate disables,
and CE IN immediately becomes high impedance if the
voltage at CE IN is a logic high. If CE IN is logic low
when reset asserts, the CE transmission gate disables
at the moment CE IN goes high or t
asserts (t
permits the current write cycle to complete during
power-down. The CE transmission gate remains dis-
abled and CE IN remains high impedance (regardless
of CE IN activity) for (t
time a reset is generated. While disabled, CE IN is high
impedance. When the CE transmission gate is enabled,
the impedance of CE IN appears as a load in series
with the load at CE OUT.
The propagation delay through the CE transmission
gate depends on V
driver connected to CE IN, and the loading on CE OUT.
The CE propagation delay is measured from the 50%
point on CE IN to the 50% point on CE OUT using a
50Ω driver and 10pF of load capacitance (Figure 14),
and is typically 5ns. For minimum propagation delay,
minimize the capacitive load at CE OUT, and use a low-
output-impedance driver.
When the CE transmission gate is enabled, the imped-
ance of CE OUT is equivalent to a resistor in series with
the source driving CE IN. In the disabled mode, the
transmission gate is off and an active pullup connects
CE OUT to OUT (Figure 12). This pullup turns off when
the transmission gate is enabled.
Figure 11. Chip-Enable Transmission Gate
CE IN
RCE
CHIP-ENABLE
GENERATOR
CONTROL
OUTPUT
), whichever occurs first (Figure 12). This
RESET
MAX6909/
MAX6910
CC
RP
, the source impedance of the
), the reset timeout period any
P
N
Chip-Enable Output
Chip-Enable Input
RCE
CC
goes below
after reset
P
OUT
CE OUT