DS1267BE-010+ Maxim Integrated, DS1267BE-010+ Datasheet - Page 4

• Manufacturer Part Number: DS1267BE-010+
• Description: Digital Potentiometer ICs Digital Sextet Potentiometer
• Manufacturer: Maxim Integrated

Specifications of DS1267BE-010+

• Resistance: 10 kOhms
• Temperature Coefficient: 750 PPM / C
• Tolerance: 20 %
• Number Of Pots: Dual
• Taps Per Pot: 256
• Digital Interface: 3-Wire
• Description/function: Dual Digital Potentiometer Chip
• Operating Supply Voltage: 4.5 V to 5.5 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-20
• Minimum Operating Temperature: - 40 C
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

DS1267B
STACKED CONFIGURATION
The potentiometers of the DS1267B can be connected in series as shown in Figure 3. This is referred to
as the stacked configuration. The stacked configuration allows the user to double the total end-to-end
resistance of the part and the number of steps to 512 (or 9 bits of resolution).
The wiper output for the combined stacked potentiometer will be taken at the S
pin, which is the
OUT
multiplexed output of the wiper of potentiometer-0 (W0) or potentiometer-1 (W1). The potentiometer
wiper selected at the S
output is governed by the setting of the stack select bit (bit 0) of the 17-bit I/O
OUT
shift register. If the stack select bit has value 0, the multiplexed output, S
, will be that of the
OUT
potentiometer-0 wiper. If the stack select bit has value 1, the multiplexed output, S
, will be that of the
OUT
potentiometer-1 wiper.
STACKED CONFIGURATION Figure 3
CASCADE OPERATION
A feature of the DS1267B is the ability to control multiple devices from a single processor. Multiple
DS1267Bs can be linked or daisy-chained as shown in Figure 4. As a data bit is entered into the I/O shift
register of the DS1267B a bit will appear at the C
output within a maximum delay of 50 nanoseconds.
OUT
The stack select bit of the DS1267B will always be the first out the part at the beginning of a transaction.
Additionally the C
pin is always active regardless of the state of
. This allows one to read the I/O
RST
OUT
shift register without changing its value.
CASCADING MULTIPLE DEVICES Figure 4
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