MSC8157ETVT1000A Freescale Semiconductor, MSC8157ETVT1000A Datasheet - Page 64

• Manufacturer Part Number: MSC8157ETVT1000A
• Description: Digital Signal Processors & Controllers - DSP, DSC Qual 8157 EN FG 1GHz -45 to 105c
• Manufacturer: Freescale Semiconductor

Specifications of MSC8157ETVT1000A

• Rohs: yes
• Core: SC3850
• Data Bus Width: 32 bit
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 0.97 V to 1.05 V
• Maximum Operating Temperature: + 105 C
• Package / Case: FCPBGA-783
• Mounting Style: SMD/SMT

Electrical Characteristics
64
At recommended operating conditions (see
At recommended operating conditions (see
At recommended operating conditions (see
At recommended operating conditions (see
Output differential voltage
(into floating load Rload = 100
Ω)
Differential resistance
Input differential voltage
Differential resistance
Output differential voltage
(into floating load Rload = 100
Ω)
De-emphasized differential
output voltage
Tx De-emphasized level
Differential resistance
Input differential
voltage
Differential resistance
Parameter
Parameter
Parameter
Table 17. Serial RapidIO Transmitter DC Specifications for Short Run at 5 Gbaud
Table 19. Serial RapidIO Transmitter DC Specifications for Long Run at 5 Gbaud
Parameter
Table 18. Serial RapidIO Receiver DC Specifications for Short Run at 5 Gbaud
Table 20. Serial RapidIO Receiver DC Specifications for Long Run at 5 Gbaud
Symbol
R_Vdiff
R_Rdin
MSC8157 Six-Core Digital Signal Processor Data Sheet, Rev. 1
T_V
T_V
Symbol
T_Vdiff
T_Rd
TX-DE-RATIO-3.5dB
TX-DE-RATIO-6.0dB
Symbol
Table
Table
Table
Table
T_Vdiff
T_Rd
4).
4).
4).
4).
Min
N/A
Min
400
80
80
Symbol
R_Rdin
R_Vdiff
Nom
Min
800
100
5.5
80
—
3
Nom
—
—
Nom
100
3.5
—
6
Max
750
120
1200
Max
120
Min
125
1200
Max
80
120
6.5
4
Units
mV
Ω
Units
mV
dB
dB
Ω
Units
Amplitude setting
L[A–J]TECR0[AMP_RED] = 0b001101
—
mV
Ω
Nom
—
—
Amplitude setting
L[A–J]TECR0[AMP_RED] =
0b000000 (with de-emphasis
disabled)
• p(n)_(y)_tx_eq_type[1:0] = 01
• p(n)_(y)_tx_ratio_post1q[3:0] = 1110
• p(n)_(y)_tx_eq_type[1:0] = 01
• p(n)_(y)_tx_ratio_post1q[3:0] = 1100
—
It is assumed that for the
R_Vdiff min specification, that
the eye can be closed at the
receiver after passing the
signal through a CEI/SRIO
Level II LR compliant channel.
—
Condition
Freescale Semiconductor
Conditions
1200
Max
120
Condition
Units
mV
Ω