IS45S16400F-5BLA1-TR ISSI, IS45S16400F-5BLA1-TR Datasheet - Page 18

• Manufacturer Part Number: IS45S16400F-5BLA1-TR
• Description: DRAM 64M (4Mx16) 200MHz Automotive Temp
• Manufacturer: ISSI

Specifications of IS45S16400F-5BLA1-TR

• Product Category: DRAM
• Rohs: yes
• Data Bus Width: 16 bit
• Package / Case: TFBGA-54
• Memory Size: 64 Mbit
• Maximum Clock Frequency: 200 MHz
• Access Time: 6 ns, 5 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V
• Maximum Operating Current: 150 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 1500

IS42S16400F
IS45S16400F
REGISTER DEFINITION
Mode Register
The mode register is used to define the specific mode
of operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in
MODE REGISTER DEFINITION.
The mode register is programmed via the LOAD MODE
REGISTER command and will retain the stored information
until it is programmed again or the device loses power.
18
MODE REGISTER DEFINITION
A11
Reserved
A10
Write Burst Mode
(1)
M9
0
1
A9
Mode
Programmed Burst Length
Single Location Access
Operating Mode
A8
M8 M7
— —
0
0
A7
Defined
M6-M0
—
Latency Mode
A6
M6 M5 M4
0
0
0
0
1
1
1
1
Mode
Standard Operation
All Other States Reserved
0
0
1
1
0
0
1
1
A5
0
1
0
1
0
1
0
1
A4
Burst Type
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved), M4- M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and
M11 are reserved for future use.
The mode register must be loaded when all banks are
idle, and the controller must wait the specified time before
initiating the subsequent operation. V iolating either of these
requirements will result in unspecified operation.
CAS Latency
M3
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
A3
Integrated Silicon Solution, Inc. — www.issi.com
2
3
Interleaved
Sequential
1. To ensure compatibility with future devices,
A2
Burst Length
Type
should program M11, M10 = "0, 0"
M2
0
0
0
0
1
1
1
1
A1
M1
0
0
1
1
0
0
1
1
M0
0
1
0
1
0
1
0
1
A0
Reserved
Reserved
Reserved
Address Bus
Mode Register (Mx)
Full Page
M3=0
1
2
4
8
Reserved
Reserved
Reserved
Reserved
M3=1
1
2
4
8
12/01/2011
Rev. I