MC56F8035VLDR Freescale Semiconductor, MC56F8035VLDR Datasheet - Page 8

• Manufacturer Part Number: MC56F8035VLDR
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLDR

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

1.1.5
1.2 56F8035/56F8025 Description
The 56F8035/56F8025 is a member of the 56800E core-based family of Digital Signal Controllers
(DSCs). It combines, on a single chip, the processing power of a DSP and the functionality of a
microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because
of its low cost, configuration flexibility, and compact program code, the 56F8035/56F8025 is well-suited
for many applications. The 56F8035/56F8025 includes many peripherals that are especially useful for
industrial control, motion control, home appliances, general-purpose inverters, smart sensors, fire and
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— Full-duplex operation
— Master and slave modes
— Four-words-deep FIFOs available on both transmitter and receiver
— Programmable Length Transactions (2 to 16 bits)
One Inter-Integrated Circuit (I
— Operates up to 400kbps
— Supports both master and slave operation
— Supports both 10-bit address mode and broadcasting mode
Three 16-bit Programmable Interval Timers (PITs)
Two analog Comparators (CMPs)
— Selectable input source includes external pins, DACs
— Programmable output polarity
— Output can drive Timer input, PWM fault input, PWM source, external pin output and trigger ADCs
— Output falling and rising edge detection able to generate interrupts
Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources
Up to 35 General-Purpose I/O (GPIO) pins with 5V tolerance
Integrated Power-On Reset (POR) and Low-Voltage Interrupt (LVI) module
Phase Lock Loop (PLL) provides a high-speed clock to the core and peripherals
Clock sources:
— On-chip relaxation oscillator
— External clock: Crystal oscillator, ceramic resonator, and external clock source
JTAG/EOnCE debug programming interface for real-time debugging
Fabricated in high-density CMOS with 5V tolerance
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
ADC smart power management
Each peripheral can be individually disabled to save power
Energy Information
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C) port
56F8035/56F8025 Data Sheet, Rev. 6
Freescale Semiconductor