LCMXO256E-3MN100C Lattice, LCMXO256E-3MN100C Datasheet - Page 20
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LCMXO256E-3MN100C
Manufacturer Part Number
LCMXO256E-3MN100C
Description
CPLD - Complex Programmable Logic Devices 256 LUTs 78 IO 1.2V -3 Spd
Manufacturer
Lattice
Datasheet
1.LCMXO1200C-5TN100C.pdf
(96 pages)
Specifications of LCMXO256E-3MN100C
Rohs
yes
Memory Type
SRAM
Number Of Macrocells
128
Maximum Operating Frequency
500 MHz
Delay Time
4.9 ns
Number Of Programmable I/os
78
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Package / Case
CSBGA-100
Mounting Style
SMD/SMT
Factory Pack Quantity
1800
Supply Current
10 mA
Supply Voltage - Max
1.26 V
Supply Voltage - Min
1.14 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO256E-3MN100C
Manufacturer:
Lattice
Quantity:
360
Company:
Part Number:
LCMXO256E-3MN100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Table 2-8. I/O Support Device by Device
Table 2-9. Supported Input Standards
Number of I/O Banks
Type of Input Buffers
Types of Output Buffers
Differential Output
Emulation Capability
PCI Support
Single Ended Interfaces
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI
Differential Interfaces
BLVDS
1. Top Banks of MachXO1200 and MachXO2280 devices only.
2. MachXO1200 and MachXO2280 devices only.
2
Single-ended
(all I/O Banks)
Single-ended buffers
with complementary
outputs (all I/O Banks)
All I/O Banks
No
1
2
MachXO256
, LVDS
Input Standard
2
, LVPECL
2
, RSDS
4
Single-ended
(all I/O Banks)
Single-ended buffers
with complementary
outputs (all I/O Banks)
All I/O Banks
No
MachXO640
2
2-17
3.3V
Yes
Yes
Yes
Yes
Yes
Yes
2.5V
Yes
Yes
Yes
Yes
Yes
VCCIO (Typ.)
8
Single-ended
(all I/O Banks)
Differential Receivers
(all I/O Banks)
Single-ended buffers
with complementary
outputs (all I/O Banks)
Differential buffers with
true LVDS outputs (50%
on left and right side)
All I/O Banks
Top side only
1.8V
Yes
Yes
Yes
Yes
Yes
Yes
MachXO1200
MachXO Family Data Sheet
1.5V
Yes
Yes
Yes
Yes
Yes
Yes
1.2V
Yes
Yes
Yes
Yes
Yes
8
Single-ended
(all I/O Banks)
Differential Receivers
(all I/O Banks)
Single-ended buffers
with complementary
outputs (all I/O Banks)
Differential buffers with
true LVDS outputs (50%
on left and right side)
Top side only
All I/O Banks
MachXO2280
Architecture