DSP56311VL160 Freescale Semiconductor, DSP56311VL160 Datasheet

DSP56311VL160

Manufacturer Part Number

DSP56311VL160

Description

Digital Signal Processors & Controllers - DSP, DSC 24 BIT DSP PBFREE

Manufacturer

Freescale Semiconductor

Datasheet

1.DSP56311VL160.pdf (96 pages)

Specifications of DSP56311VL160

Rohs

yes

Core

DSP56000

Data Bus Width

24 bit

Program Memory Size

128 KB

Maximum Clock Frequency

150 MHz

Number Of Programmable I/os

Number Of Timers

Device Million Instructions Per Second

300 MIPs

Operating Supply Voltage

3.3 V

Package / Case

MAP-BGA-196

Mounting Style

SMD/SMT

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Freescale Semiconductor

Technical Data

DSP56311

24-Bit Digital Signal Processor

The Freescale DSP56311, a member of the DSP56300 DSP family, supports network applications with general filtering

operations. The Enhanced Filter Coprocessor (EFCOP) executes filter algorithms in parallel with core operations enhancing

signal quality with no impact on channel throughput or total channels supported. The result is increased overall performance.

Like the other DSP56300 family members, the DSP56311 uses a high-performance, single-clock-cycle-per- instruction engine

(DSP56000 code-compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA)

controller (see Figure 1). The DSP56311 performs at up to 150 million multiply-accumulates per second (MMACS), attaining

up to 300 MMACS when the EFCOP is in use. It operates with an internal 150 MHz clock with a 1.8 volt core and

independent 3.3 volt input/output (I/O) power.

PINIT/NMI

RESET

EXTAL

XTAL

SCI

Bootstrap

Generator

Internal

Switch

ROM

Data

Clock

Bus

Six Channel

Generation

DMA Unit

Address

Unit

Timer

Triple

PLL

PCAP

Controller

Program

HI08

Interrupt

ESSI

Expansion Area

Peripheral

MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

Controller

Program

Decode

EFCOP

Figure 1. DSP56311 Block Diagram

Generator

Program

Address

1024 × 24 bits

32 K × 24 bits

31 K × 24 bits

Instruction

Program

Cache

RAM

and

DSP56300

DDB

YDB

XDB

PDB

GDB

24-Bit

Core

24 × 24 + 56 → 56-bit MAC

XAB

DAB

YAB

PAB

Two 56-bit Accumulators

56-bit Barrel Shifter

48 K × 24 bits

Data ALU

X Data

RAM

Memory Expansion Area

48 K × 24 bits

Y Data

RAM

Management

OnCE™

I - Cache

Interface

External

Address

External

Power

Control

External

JTAG

Switch

Data

Bus

and

Bus

Address

Control

Data

The DSP56311 is intended

for applications requiring a

large amount of internal

memory, such as networking

and wireless infrastructure

applications. The onboard

EFCOP can accelerate

general filtering applications,

such as echo-cancellation

applications, correlation, and

general-purpose convolution-

based algorithms.

Rev. 8 includes the following

changes:

• Adds lead-free packaging and

part numbers.

What’s New?

Rev. 8, 2/2005

DSP56311

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