LC4512C-10FTN256I Lattice, LC4512C-10FTN256I Datasheet - Page 4

• Manufacturer Part Number: LC4512C-10FTN256I
• Description: CPLD - Complex Programmable Logic Devices ispJTAG 1.8V 10nsIND 512MC 208 I/O
• Manufacturer: Lattice

Specifications of LC4512C-10FTN256I

• Rohs: yes
• Memory Type: EEPROM
• Number Of Macrocells: 512
• Maximum Operating Frequency: 125 MHz
• Delay Time: 10 ns
• Number Of Programmable I/os: 208
• Operating Supply Voltage: 1.8 V
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Package / Case: FTBGA
• Mounting Style: SMD/SMT
• Number Of Product Terms Per Macro: 80
• Factory Pack Quantity: 450
• Supply Current: 4 mA
• Supply Voltage - Max: 1.95 V
• Supply Voltage - Min: 1.65 V

Lattice Semiconductor
Figure 2. Generic Logic Block
AND Array
The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are
used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con-
nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic
allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and
Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being
fed to the macrocells.
Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0.
There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND
Array.
from GRP
36 Inputs
4
Generator
Clock
ispMACH 4000V/B/C/Z Family Data Sheet
To GRP
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
Output Enable
Product Term
Sharing
To