LC4512C-75FTN256C Lattice, LC4512C-75FTN256C Datasheet - Page 43

• Manufacturer Part Number: LC4512C-75FTN256C
• Description: CPLD - Complex Programmable Logic Devices ispJTAG 1.8V 7.5ns 512MC 208 I/O
• Manufacturer: Lattice

Specifications of LC4512C-75FTN256C

• Rohs: yes
• Memory Type: EEPROM
• Number Of Macrocells: 512
• Maximum Operating Frequency: 178.57 MHz
• Delay Time: 7.5 ns
• Number Of Programmable I/os: 208
• Operating Supply Voltage: 1.8 V
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Package / Case: FTBGA
• Mounting Style: SMD/SMT
• Number Of Product Terms Per Macro: 80
• Factory Pack Quantity: 450
• Supply Current: 4 mA
• Supply Voltage - Max: 1.95 V
• Supply Voltage - Min: 1.65 V

Lattice Semiconductor
ispMACH 4000V/B/C/Z Power Supply and NC Connections
VCC
VCCO0
VCCO (Bank 0)
VCCO1
VCCO (Bank 1)
GND
GND (Bank 0)
GND (Bank 1)
NC
1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with
2. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise.
3. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order
the bank shown.
ascending horizontally.
Signal
11, 33
12, 34
5
6
28
27
—
44-pin TQFP
2
5
12, 36
6
30
13, 37
29
—
48-pin TQFP
2
K2, A9
F3
E8
H3, C8
D3
G8
4032Z: A8, B10, E1,
E3, F8, F10, J1, K3
43
56-ball csBGA
ispMACH 4000V/B/C/Z Family Data Sheet
3
25, 40, 75, 90
13, 33, 95
45, 63, 83
1, 26, 51, 76
7, 18, 32, 96
46, 57, 68, 82
—
100-pin TQFP
1
2
32, 51, 96, 115
3, 17, 30, 41, 122
58, 67, 81, 94, 105
1, 33, 65, 97
10, 24, 40, 113, 123
49, 59, 74, 88, 104
—
128-pin TQFP
2