dsPIC33FJ32MC102-I/SO Microchip Technology, dsPIC33FJ32MC102-I/SO Datasheet - Page 239
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dsPIC33FJ32MC102-I/SO
Manufacturer Part Number
dsPIC33FJ32MC102-I/SO
Description
Digital Signal Processors & Controllers - DSP, DSC 16bit Mtr Cnt Fam 16 MIPS 32KBFLSH 2KBRAM
Manufacturer
Microchip Technology
Type
dsPIC33FJ32(GP/MC)101/102/104r
Datasheet
1.DSPIC33FJ32GP102-ISO.pdf
(386 pages)
Specifications of dsPIC33FJ32MC102-I/SO
Rohs
yes
Core
dsPIC33F
Data Bus Width
16 bit
Program Memory Size
32 KB
Data Ram Size
2 KB
Maximum Clock Frequency
7.37 MHz, 32 kHz
Number Of Programmable I/os
21
Number Of Timers
5 x 16-bit, 2 x 32-bit
Device Million Instructions Per Second
16 MIPs
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Package / Case
QFN-28
Mounting Style
SMD/SMT
Family / Core
dsPIC33FJ32(GP/MC)101/102/104
Interface Type
I2C, SPI, UART
Minimum Operating Temperature
- 40 C
On-chip Adc
Yes
Product
DSPs
Program Memory Type
Flash
Supply Current
10 mA
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REGISTER 20-5:
2011-2012 Microchip Technology Inc.
Legend:
R = Readable bit
-n = Value at POR
bit 15-7
bit 6-4
bit 3
bit 2-0
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
bit 15
bit 7
U-0
U-0
—
—
Unimplemented: Read as ‘0’
CFSEL<2:0>: Comparator Filter Input Clock Select bits
111 = Reserved
110 = Reserved
101 = Timer3
100 = Timer2
011 = Reserved
010 = PWM Special Event Trigger
001 = F
000 = F
CFLTREN: Comparator Filter Enable bit
1 = Digital filter is enabled
0 = Digital filter is disabled
CFDIV<2:0>: Comparator Filter Clock Divide Select bits
111 = Clock Divide 1:128
110 = Clock Divide 1:64
101 = Clock Divide 1:32
100 = Clock Divide 1:16
011 = Clock Divide 1:8
010 = Clock Divide 1:4
001 = Clock Divide 1:2
000 = Clock Divide 1:1
R/W-0
U-0
—
CMxFLTR: COMPARATOR x FILTER CONTROL REGISTER
OSC
CY
CFSEL<2:0>
W = Writable bit
‘1’ = Bit is set
R/W-0
U-0
—
R/W-0
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CFLTREN
R/W-0
U-0
—
R/W-0
U-0
—
CFDIV<2:0>
x = Bit is unknown
R/W-0
U-0
—
DS70652E-page 239
R/W-0
bit 8
bit 0
U-0
—
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