dsPIC33FJ32GP104-I/PT Microchip Technology, dsPIC33FJ32GP104-I/PT Datasheet - Page 191

• Manufacturer Part Number: dsPIC33FJ32GP104-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Gen Prp Fam16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32GP104-I/PT

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

REGISTER 15-10: PxFLTBCON: PWMx FAULT B CONTROL REGISTER
 2011-2012 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13-8
bit 7
bit 6-3
bit 2
bit 1
bit 0
Note 1:
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FLTBM
R/W-0
U-0
—
2:
3:
4:
Comparator outputs are not internally connected to the PWM Fault control logic. If using the Comparator
modules for Fault generation, the user must externally connect the desired comparator output pin to the
dedicated FLTA1 or FLTB1 input pin.
Refer to
The PxFLTACON register is a write-protected register. Refer to
for more information on the unlock sequence.
During any Reset event, FLTB1 is enabled by default and must be cleared as described in
“PWM
Unimplemented: Read as ‘0’
FBOVxH<3:1>:FBOVxL<3:1>: Fault Input B PWM Override Value bits
1 = The PWM output pin is driven active on an external Fault input event
0 = The PWM output pin is driven inactive on an external Fault input event
FLTBM: Fault B Mode bit
1 = The Fault B input pin functions in the Cycle-by-Cycle mode
0 = The Fault B input pin latches all control pins to the programmed states in PxFLTBCON<13:8>
Unimplemented: Read as ‘0’
FBEN3: Fault Input B Enable bit
1 = PWMxH3/PWMxL3 pin pair is controlled by Fault Input B
0 = PWMxH3/PWMxL3 pin pair is not controlled by Fault Input B
FBEN2: Fault Input B Enable bit
1 = PWMxH2/PWMxL2 pin pair is controlled by Fault Input B
0 = PWMxH2/PWMxL2 pin pair is not controlled by Fault Input B
FBEN1: Fault Input B Enable bit
1 = PWMxH1/PWMxL1 pin pair is controlled by Fault Input B
0 = PWMxH1/PWMxL1 pin pair is not controlled by Fault Input B
Faults”.
Table 15-1
U-0
U-0
—
—
W = Writable bit
‘1’ = Bit is set
for FLTB1 implementation details.
FBOV3H
R/W-0
U-0
—
FBOV3L
R/W-0
U-0
—
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
FBOV2H
R/W-0
U-0
—
Section 15.3 “Write-Protected Registers”
FBOV2L
FBEN3
R/W-0
R/W-1
(1,2,3,4)
x = Bit is unknown
FBOV1H
FBEN2
R/W-0
R/W-1
DS70652E-page 191
Section 15.2
FBOV1L
FBEN1
R/W-0
R/W-1
bit 8
bit 0