LC4512C-10FT256I Lattice, LC4512C-10FT256I Datasheet - Page 8
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LC4512C-10FT256I
Manufacturer Part Number
LC4512C-10FT256I
Description
CPLD - Complex Programmable Logic Devices ispJTAG 1.8V 10nsIND 512MC 208 I/O
Manufacturer
Lattice
Datasheet
1.LC4512C-10FT256I.pdf
(99 pages)
Specifications of LC4512C-10FT256I
Memory Type
EEPROM
Number Of Macrocells
512
Maximum Operating Frequency
125 MHz
Delay Time
10 ns
Number Of Programmable I/os
208
Operating Supply Voltage
1.8 V
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Package / Case
FTBGA
Mounting Style
SMD/SMT
Number Of Product Terms Per Macro
80
Factory Pack Quantity
450
Supply Current
4 mA
Supply Voltage - Max
1.95 V
Supply Voltage - Min
1.65 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LC4512C-10FT256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Clock Enable Multiplexer
Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the fol-
lowing four sources:
Initialization Control
The ispMACH 4000 family architecture accommodates both block-level and macrocell-level set and reset capability.
There is one block-level initialization term that is distributed to all macrocell registers in a GLB. At the macrocell
level, two product terms can be “stolen” from the cluster associated with a macrocell to be used for set/reset func-
tionality. A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing
flexibility.
Note that the reset/preset swapping selection feature affects power-up reset as well. All flip-flops power up to a
known state for predictable system initialization. If a macrocell is configured to SET on a signal from the block-level
initialization, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a
signal from the block-level initialization or is not configured for set/reset, then that macrocell will RESET on power-
up. To guarantee initialization values, the V
delay time has elapsed.
GLB Clock Generator
Each ispMACH 4000 device has up to four clock pins that are also routed to the GRP to be used as inputs. These
pins drive a clock generator in each GLB, as shown in Figure 6. The clock generator provides four clock signals that
can be used anywhere in the GLB. These four GLB clock signals can consist of a number of combinations of the
true and complement edges of the global clock signals.
Figure 6. GLB Clock Generator
• Block CLK2
• Block CLK3
• PT Clock
• PT Clock Inverted
• Shared PT Clock
• Ground
• PT Initialization/CE
• PT Initialization/CE Inverted
• Shared PT Clock
• Logic High
CLK0
CLK1
CLK2
CLK3
CC
rise must be monotonic, and the clock must be inactive until the reset
8
ispMACH 4000V/B/C/Z Family Data Sheet
Block CLK0
Block CLK1
Block CLK2
Block CLK3