LC4256C-5FT256AC Lattice, LC4256C-5FT256AC Datasheet - Page 22
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LC4256C-5FT256AC
Manufacturer Part Number
LC4256C-5FT256AC
Description
CPLD - Complex Programmable Logic Devices 256MC 128 I/O ispJTAG 1.8V 5ns
Manufacturer
Lattice
Datasheet
1.LC4384C-5FTN256C.pdf
(99 pages)
Specifications of LC4256C-5FT256AC
Memory Type
EEPROM
Number Of Macrocells
256
Maximum Operating Frequency
227.27 MHz
Delay Time
5 ns
Number Of Programmable I/os
160
Operating Supply Voltage
1.8 V
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Package / Case
FTBGA
Mounting Style
SMD/SMT
Number Of Product Terms Per Macro
80
Factory Pack Quantity
450
Supply Current
2.5 mA
Supply Voltage - Max
1.95 V
Supply Voltage - Min
1.65 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LC4256C-5FT256AC
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
ispMACH 4000V/B/C External Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
f
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.
2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
Parameter
PD
PD_MC
S
ST
SIR
SIRZ
H
HT
HIR
HIRZ
CO
R
RW
PTOE/DIS
GPTOE/DIS
GOE/DIS
CW
GW
WIR
MAX
MAX
4
(Ext.)
5-PT bypass combinatorial propagation
delay
20-PT combinatorial propagation delay
through macrocell
GLB register setup time before clock
GLB register setup time before clock
with T-type register
GLB register setup time before clock,
input register path
GLB register setup time before clock
with zero hold
GLB register hold time after clock
GLB register hold time after clock with
T-type register
GLB register hold time after clock, input
register path
GLB register hold time after clock, input
register path with zero hold
GLB register clock-to-output delay
External reset pin to output delay
External reset pulse duration
Input to output local product term output
enable/disable
Input to output global product term
output enable/disable
Global OE input to output enable/disable
Global clock width, high or low
Global gate width low (for low
transparent) or high (for high transparent)
Input register clock width, high or low
Clock frequency with internal feedback
Clock frequency with external feedback,
[1/ (t
S
+ t
CO
)]
Description
1, 2, 3
Over Recommended Operating Conditions
Min.
2.0
0.7
1.7
0.0
0.0
0.9
0.0
1.5
1.1
1.8
1.1
1.1
—
—
—
—
—
—
—
—
—
-25
22
Max.
400
250
2.5
3.2
2.2
3.5
4.0
5.0
3.0
—
—
—
—
—
—
—
—
—
—
—
—
ispMACH 4000V/B/C/Z Family Data Sheet
Min.
1.8
2.0
1.0
2.0
0.0
0.0
1.0
0.0
1.5
1.3
1.3
1.3
—
—
—
—
—
—
—
—
—
-27
Max.
333
222
2.7
3.5
2.7
4.0
4.5
6.5
3.5
—
—
—
—
—
—
—
—
—
—
—
—
Min.
2.0
2.2
1.0
2.0
0.0
0.0
1.0
0.0
1.5
1.3
1.3
1.3
—
—
—
—
—
—
—
—
—
-3
Max.
322
212
3.0
3.8
2.7
4.4
5.0
8.0
4.0
—
—
—
—
—
—
—
—
—
—
—
—
Min.
2.0
2.2
1.0
2.0
0.0
0.0
1.0
0.0
1.5
1.3
1.3
1.3
—
—
—
—
—
—
—
—
—
-35
Max.
322
212
3.5
4.2
2.7
5.5
8.0
4.5
4.5
—
—
—
—
—
—
—
—
—
—
—
-
Timing v.3.2
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns