MAX11056ECB+T Maxim Integrated, MAX11056ECB+T Datasheet - Page 14

• Manufacturer Part Number: MAX11056ECB+T
• Description: Analog to Digital Converters - ADC 14Bit 8Ch Simult Sampling
• Manufacturer: Maxim Integrated

Specifications of MAX11056ECB+T

• Rohs: yes
• Number Of Channels: 8
• Architecture: SAR
• Conversion Rate: 250 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended
• Snr: 92.3 dB
• Interface Type: Parallel
• Operating Supply Voltage: 2.7 V to 5.25 V, 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 3478 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 8
• Voltage Reference: 4.096 V

4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
14
23, 28, 32, 38,
24, 29, 35, 46,
25, 30, 36, 45,
43, 49, 53, 58
MAX11054
(TQFP-EP)
8, 22, 59
9, 21, 60
52, 57
51, 56
26, 55
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
23, 28, 32, 38,
24, 29, 35, 46,
25, 30, 36, 45,
43, 49, 53, 58
MAX11055
(TQFP-EP)
8, 22, 59
9, 21, 60
52, 57
51, 56
26, 55
PIN
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
23, 28, 32, 38,
24, 29, 35, 46,
25, 30, 36, 45,
43, 49, 53, 58
MAX11056
(TQFP-EP)
8, 22, 59
9, 21, 60
52, 57
51, 56
26, 55
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
RDC_SENSE
DB1/CR3
DB0/CR2
CONVST
AGNDS
NAME
DGND
AGND
DVDD
SHDN
AVDD
DB12
DB11
DB10
EOC
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
CR1
CR0
14-Bit Parallel Data Bus Digital Output Bit 12
14-Bit Parallel Data Bus Digital Output Bit 11
14-Bit Parallel Data Bus Digital Output Bit 10
14-Bit Parallel Data Bus Digital Output Bit 9
14-Bit Parallel Data Bus Digital Output Bit 8
14-Bit Parallel Data Bus Digital Output Bit 7
14-Bit Parallel Data Bus Digital Output Bit 6
Digital Ground
Digital Supply. Bypass to DGND with a 0.1µF capacitor
at each DVDD input.
14-Bit Parallel Data Bus Digital Output Bit 5
14-Bit Parallel Data Bus Digital Output Bit 4
14-Bit Parallel Data Bus Digital Output Bit 3
14-Bit Parallel Data Bus Digital Output Bit 2
14-Bit Parallel Data Bus Digital Output Bit 1/
Configuration Register Input Bit 3
14-Bit Parallel Data Bus Digital Output Bit 0/
Configuration Register Input Bit 2
Configuration Register Input Bit 1
Configuration Register Input Bit 0
Active-Low End-of-Conversion Output. EOC goes low
when conversion is completed. EOC goes high when a
conversion is initiated.
C onver t S tar t Inp ut. Ri si ng ed g e of C ON V S T end s
sam p l e and star ts a conver si on on the cap tur ed sam p l e.
The AD C i s i n acq ui si ti on m od e w hen C ON V S T i s l ow
and C ON V S T m od e = 0.
Shutdown Input. If SHDN is held high, the entire device
will enter and stay in a low-current state. Contents of
the configuration register are not lost when in the
shutdown mode.
Signal Ground. Connect all AGND and AGNDS inputs
together on PCB.
Analog Supply Input. Bypass AVDD to AGND with a
0.1µF capacitor at each AVDD input.
Analog Ground. Connect all AGND inputs together.
Refer ence Buffer S ense Feed b ack. C onnect to RD C p l ane.
Pin Description (continued)
FUNCTION
Maxim Integrated