S9S12G96F0MLF Freescale Semiconductor, S9S12G96F0MLF Datasheet - Page 689

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S9S12G96F0MLF

Manufacturer Part Number
S9S12G96F0MLF
Description
16-bit Microcontrollers - MCU 16BIT 96K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12G96F0MLF

Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
96 KB
Data Ram Size
8192 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT

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20.4.6
20.4.6.1
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI
control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in
SCI data register high (SCIDRH) is the ninth bit (bit 8).
20.4.6.2
During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register
is the read-only buffer between the internal data bus and the receive shift register.
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the
SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set,
Freescale Semiconductor
From TXD Pin
or Transmitter
SCRXD
LOOPS
RSRC
Receiver
Receiver Character Length
Character Reception
RXPOL
Control
SBR12:SBR0
Loop
Clock
Bus
Baud Divider
Figure 20-20. SCI Receiver Block Diagram
MC9S12G Family Reference Manual, Rev.1.23
WAKE
RAF
RE
ILT
PE
PT
M
Recovery
Detect Logic
Data
Detect Logic
Active Edge
Break
BRKDFE
Checking
Wakeup
Parity
Logic
Internal Bus
H
RXEDGIE
RXEDGIF
BRKDIF
BRKDIE
8
RDRF
11-Bit Receive Shift Register
7
OR
Serial Communication Interface (S12SCIV5)
SCI Data Register
6
5
4
FE
NF
PE
3
R8
IDLE
ILIE
RIE
2
Break IRQ
RX Active Edge IRQ
1
0
L
RWU
RDRF/OR
Idle IRQ
IRQ
691

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