MAX1266AEEI Maxim Integrated, MAX1266AEEI Datasheet - Page 11

• Manufacturer Part Number: MAX1266AEEI
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1266AEEI

• Number Of Channels: 6/3
• Architecture: SAR
• Conversion Rate: 420 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 70 dB
• Interface Type: Parallel
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Package / Case: QSOP-28
• Maximum Power Dissipation: 667 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time,
t
the signal, and is also the minimum time required for
the signal to be acquired. Calculate this with the follow-
ing equation:
where R
R
the ADC’s input capacitance. Source impedances
below 3kΩ have no significant impact on the MAX1266/
MAX1268s’ AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Together with the input impedance, this capacitor
forms an RC filter, limiting the ADC’s signal bandwidth.
The MAX1266/MAX1268 T/H stage offers a 350kHz full-
linear and a 6MHz full-power bandwidth. This makes it
possible to digitize high-speed transients and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid high-frequency signals being aliased into the fre-
quency band of interest, anti-alias filtering is recom-
mended.
Initiate a conversion by writing a control byte, which
selects the multiplexer channel and configures the
MAX1266/MAX1268 for either unipolar or bipolar opera-
tion. A write pulse (WR + CS) can either start an acqui-
sition interval or initiate a combined acquisition plus
conversion. The sampling interval occurs at the end of
the acquisition interval. The ACQMOD (acquisition
mode) bit in the input control byte (Table 1) offers two
options for acquiring the signal: an internal and an
external acquisition. The conversion period lasts for 13
clock cycles in either the internal or external clock or
acquisition mode. Writing a new control byte during a
conversion cycle aborts the conversion and starts a
new acquisition interval.
Select internal acquisition by writing the control byte
with the ACQMOD bit cleared (ACQMOD = 0). This
causes the write pulse to initiate an acquisition interval
whose duration is internally timed. Conversion starts
when this acquisition interval (three external clock
cycles or approximately 1µs in internal clock mode)
ACQ
IN
(800Ω) is the input resistance, and C
, is the maximum time the device takes to acquire
S
with +2.5V Reference and Parallel Interface
is the source impedance of the input signal,
t
ACQ
______________________________________________________________________________________
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
= 9(R
S
Starting a Conversion
+ R
IN
Input Bandwidth
Internal Acquisition
)C
IN
IN
(12pF) is
ends (Figure 4). Note that, when the internal acquisition
is combined with the internal clock, the aperture jitter
can be as high as 200ps. Internal clock users wishing
to achieve the 50ps jitter specification should always
use external acquisition mode.
Use external acquisition mode for precise control of the
sampling aperture and/or dependent control of acquisi-
tion and conversion times. The user controls acquisition
and start-of-conversion with two separate write pulses.
The first pulse, written with ACQMOD = 1, starts an
acquisition interval of indeterminate length. The second
write pulse, written with ACQMOD = 0 (all other bits in
control byte unchanged), terminates acquisition and
starts conversion on WR rising edge (Figure 5).
The address bits for the input multiplexer must have the
same values on the first and second write pulse.
Power-down mode bits (PD0, PD1) can assume new
values on the second write pulse (see Power-Down
Modes section). Changing other bits in the control byte
corrupts the conversion.
A standard interrupt signal, INT, is provided to allow the
MAX1266/MAX1268 to flag the µP when the conversion
has ended and a valid result is available. INT goes low
when the conversion is complete and the output data is
ready (Figures 4 and 5). It returns high on the first read
cycle or if a new control byte is written.
The MAX1266/MAX1268 operate with either an internal
or an external clock. Control bits D6 and D7 select
either internal or external clock mode. The part retains
the last-requested clock mode if a power-down mode is
selected in the current input word. For both internal and
external clock mode, internal or external acquisition
can be used. At power-up, the MAX1266/MAX1268
enter the default external clock mode.
Select internal clock mode to release the µP from the
burden of running the SAR conversion clock. Bit D7 of
the control byte must be set to 1 and bit D6 must be set
to zero. The internal clock frequency is then selected,
resulting in a conversion time of 3.6µs. When using the
internal clock mode, tie the CLK pin either high or low
to prevent the pin from floating.
Reading a Conversion
Selecting Clock Mode
External Acquisition
Internal Clock Mode
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