MAX1169BEUD Maxim Integrated, MAX1169BEUD Datasheet - Page 15

• Manufacturer Part Number: MAX1169BEUD
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1169BEUD

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 58 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended
• Snr: 90 dB
• Interface Type: I2C, Serial
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TSSOP-14
• Maximum Power Dissipation: 864 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

MAX1169 is in HS mode. The master must then send a
repeated START followed by a slave address to initiate
HS mode communication. If the master generates a
STOP condition, the MAX1169 returns to F/S mode.
Initiate a read cycle to begin a conversion. A read
cycle begins with the master issuing a START condition
followed by 7 address bits and 1 read bit (R/W). The
standard I
1 to read from a device; however, since the MAX1169
does not require setup or configuration, the read mode
is inherent and R/W controls power-down (see the
Internal Reference Shutdown section). If the address
byte is successfully received, the MAX1169 (slave)
issues an acknowledge and begins conversion.
As seen in Figure 11, the MAX1169 holds SCL low dur-
ing conversion. When the conversion is complete, SCL
is released and the master can clock data out of the
device. The most significant byte of the conversion is
available first and contains D15 to D8. The least signifi-
cant byte contains D7 to D0. Data can be continuously
converted as long as the master acknowledges the
conversion results. Issuing a not acknowledge frees the
bus, allowing the master to generate a STOP or repeat-
ed START.
Figure 9. MAX1169 Slave Address Byte
Figure 10. F/S-Mode to HS-Mode Transfer
SDA
SDA
SCL
S
2
C-compatible interface requires that R/W =
S
______________________________________________________________________________________
0
1
1
0
0
2
Data Byte (Read Cycle)
58.6ksps, 16-Bit, 2-Wire Serial ADC
2
1
0
3
3
1
0
4
F/S MODE
ADD3
4
1
5
When power is first applied, internal power-on reset cir-
cuitry activates the MAX1169 in shutdown. When the
internal reference is used, allow 12ms for the reference
to settle when C
The MAX1169 automatic shutdown reduces the supply
current to less than 0.6μA between conversions. The
MAX1169 I
When the MAX1169 receives a valid slave address, the
device powers up. The device is then powered down
again when the conversion is complete. The automatic
shutdown function does not change with internal or
external reference. When the internal reference is cho-
sen, the internal reference remains active between con-
versions unless internal reference shutdown is requested
(see the Internal Reference Shutdown section).
The R/W bit of the slave address controls the MAX1169
internal reference shutdown. In external reference
mode (REFADJ = AVDD), R/W is a don’t care. In inter-
nal reference mode, setting R/W = 1 places the device
in normal operation and setting R/W = 0 prepares the
internal reference for shutdown.
ADD2
5
X
6
ADD1
2
in a 14-Pin TSSOP
6
C-compatible interface is always active.
Applications Information
X
REF
7
Internal Reference Shutdown
ADD0
= 10μF and C
7
X
8
ACKNOWLEDGE
Automatic Shutdown
R/W
8
REFADJ
Power-On Reset
A
9
A
9
HS MODE
= 0.1μF.
Sr
15