MAX192ACWP Maxim Integrated, MAX192ACWP Datasheet - Page 6

• Manufacturer Part Number: MAX192ACWP
• Description: Analog to Digital Converters - ADC Integrated Circuits (ICs)
• Manufacturer: Maxim Integrated

Specifications of MAX192ACWP

• Number Of Channels: 8
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: Yes
• Interface Type: 4-Wire (SPI, Microwire, QSPI, TMS320)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOIC-20 Wide
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Factory Pack Quantity: 36
• Voltage Reference: 4.096 V

Low-Power, 8-Channel,
Serial 10-Bit ADCs
Figure 1. Load Circuits for Enable Time
6
DOUT
a) High-Z to V
9, 13
________________________________________________________________________________________________
PIN
1–8
10
11
12
14
15
16
17
18
19
20
3k
OH
DGND
and V
CH0–CH7
REFADJ
SSTRB
NAME
DGND
AGND
SHDN
DOUT
SCLK
VREF
OL
V
DIN
CS
DD
to V
OH
C
LOAD
Sampling Analog Inputs
Analog Ground. Also IN- Input for single-enabled conversions. Connect both AGND pins to
analog ground.
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX192 down to 10µA (max) supply cur-
rent, otherwise the MAX192 is fully operational. Pulling SHDN high puts the reference-buffer amplifi-
er in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in external
compensation mode.
Reference Voltage for analog-to-digital conversion. Also, Output of the Reference Buffer Amplifier.
Add a 4.7µF capacitor to ground when using external compensation mode. Also functions as an
input when used with a precision external reference.
Reference-Buffer Amplifier Input. To disable the reference-buffer amplifier, tie REFADJ to V
Digital Ground
Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is
high.
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX192 begins the A/D
conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses high
for one clock period before the MSB decision. SSTRB is high impedance when CS is high
(external mode).
Serial Data Input. Data is clocked in at the rising edge of SCLK.
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT
is high impedance.
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)
Positive Supply Voltage, +5V ±5%
b) High-Z to V
DOUT
+5V
OL
and V
3k
C
DGND
LOAD
OH
to V
OL
Figure 2. Load Circuits for Disabled Time
DOUT
FUNCTION
3k
a) V
OH
DGND
to High-Z
C
LOAD
DOUT
Pin Description
b) V
OL
+3V
to High-Z
3k
C
DGND
LOAD
DD
.