MAX1064ACEG Maxim Integrated, MAX1064ACEG Datasheet - Page 17

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MAX1064ACEG

Manufacturer Part Number
MAX1064ACEG
Description
Analog to Digital Converters - ADC
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX1064ACEG

Number Of Channels
4/2
Architecture
SAR
Conversion Rate
400 KSPs
Resolution
10 bit
Input Type
Single-Ended/Pseudo-Differential
Snr
61 dB
Interface Type
Serial
Operating Supply Voltage
2.7 V to 5.5 V, 5 V
Maximum Operating Temperature
+ 70 C
Package / Case
QSOP-24
Maximum Power Dissipation
762 mW
Minimum Operating Temperature
0 C
Number Of Converters
1
Voltage Reference
2.5 V
High-frequency noise in the power supply (V
influence the proper operation of the ADC’s fast com-
parator. Bypass V
of two parallel capacitors, 0.1µF and 4.7µF, located as
close as possible to the MAX1060/MAX1064s’ power-
supply pin. Minimize capacitor lead length for best sup-
ply-noise rejection, and add an attenuation resistor (5Ω)
if the power supply is extremely noisy.
__________________________Definitions
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The
Figure 10. Timing Diagram for Fastest Conversion
D7–D0
STATE
HBEN
CLK
WR
RD
with +2.5V Reference and Parallel Interface
CONTROL
BYTE
1
DD
______________________________________________________________________________________
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
ACQUISITION
D7–D0 D9–D8
to the star ground with a network
2
LOW
BYTE
3
HIGH
BYTE
Integral Nonlinearity
SAMPLING INSTANT
4
5
6
DD
7
) could
8
9
10
MAX1060/MAX1064s’ INL is measured using the end-
point method.
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Aperture jitter (t
the time between the samples.
Aperture delay (t
edge of the sampling clock and the instant when an
actual sample is taken.
CONTROL BYTE
CONVERSION
11
12
13
AJ
) is the sample-to-sample variation in
AD
14
) is the time between the rising
15
Differential Nonlinearity
16
LOW
BYTE
Aperture Delay
Aperture Jitter
D7–D0 D9–D8
ACQUISITION
HIGH
BYTE
17

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