MAX1289EKA-T Maxim Integrated, MAX1289EKA-T Datasheet - Page 7

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MAX1289EKA-T

Manufacturer Part Number
MAX1289EKA-T
Description
Analog to Digital Converters - ADC
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX1289EKA-T

Number Of Channels
1
Architecture
SAR
Conversion Rate
150 KSPs
Resolution
12 bit
Input Type
Single-Ended
Snr
No
Interface Type
3-Wire, Microwire, QSPI, Serial, SPI
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOT-23
Maximum Power Dissipation
696 mW
Minimum Operating Temperature
- 40 C
Number Of Converters
1
Voltage Reference
External
The MAX1286–MAX1289 ADCs use a successive-
approximation conversion (SAR) technique and an on-
chip track-and-hold (T/H) structure to convert an
analog signal into a 12-bit digital result.
Figure 3. Simplified Functional Diagram
PIN
1
2
3
4
5
6
7
8
CNVST
(AIN+)
(AIN-)
150ksps, 12-Bit, 2-Channel Single-Ended, and
SCLK
AIN1
AIN2
REF
MAX1286
MAX1287
CNVST
DOUT
SCLK
AIN1
AIN2
GND
V
REF
EP
DD
( ) ARE FOR MAX1288/MAX1289
MAX1286–MAX1289
NAME
INPUT SHIFT
REGISTER
_______________________________________________________________________________________
MAX1288
MAX1289
T/H
CNVST
Detailed Description
DOUT
SCLK
AIN+
GND
AIN-
V
REF
EP
DD
OSCILLATOR
CONTROL
Positive Supply Voltage. +2.7V to +3.6V (MAX1287/MAX1289); +4.75V to +5.25V
(MAX1286/MAX1288). Bypass with a 0.1µF capacitor to GND.
Analog Input Channel 1 (MAX1286/MAX1287) or Positive Analog Input (MAX1288/MAX1289)
Analog Input Channel 2 (MAX1286/MAX1287) or Negative Analog Input (MAX1288/MAX1289)
Ground
External Reference Voltage Input. Sets the analog voltage range. Bypass with a 0.1µF
capacitor to GND.
Conversion Start. A rising edge powers up the IC and places it in track mode. At the falling
edge of CNVST, the device enters hold mode and begins conversion. CNVST also selects the
input channel (MAX1286/MAX1287) or input polarity (MAX1288/MAX1289).
Serial Data Output. DOUT transitions the falling edge of SCLK. DOUT goes low at the start of a
conversion and presents the MSB at the completion of a conversion. DOUT goes high
impedance once data has been fully clocked out.
Exposed Pad. Connect the exposed pad to ground or leave unconnected.
Serial Clock Input. Clocks out data at DOUT MSB first.
12-BIT
ADC
SAR
1-Channel True-Differential ADCs
DOUT
The serial interface provides easy interfacing to micro-
processors (µPs). Figure 3 shows the simplified internal
structure for the MAX1286/MAX1287 (2 channels, sin-
gle ended) and the MAX1288/MAX1289 (1 channel,
true differential).
The equivalent circuit of Figure 4 shows the
MAX1286–MAX1289s’ input architecture, which is com-
posed of a T/H, input multiplexer, comparator, and
switched-capacitor DAC. The T/H enters its tracking
mode on the rising edge of CNVST. The positive input
capacitor is connected to AIN1 or AIN2 (MAX1286/
MAX1287) or AIN+ (MAX1288/MAX1289). The negative
input capacitor is connected to GND (MAX1286/
MAX1287) or AIN- (MAX1288/MAX1289). The T/H enters
its hold mode on the falling edge of CNVST and the dif-
ference between the sampled positive and negative
input voltages is converted. The time required for the
T/H to acquire an input signal is determined by how
quickly its input capacitance is charged. If the input sig-
nal’s source impedance is high, the acquisition time
lengthens, and CNVST must be held high for a longer
period of time. The acquisition time, t
mum time needed for the signal to be acquired, plus the
power-up time. It is calculated by the following equation:
FUNCTION
t
ACQ
True-Differential Analog Input T/H
= 9 x (R
S
+ R
IN
) x 24pF + t
Pin Description
ACQ
PWR
, is the maxi-
7

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