MAX1133BEAP-T Maxim Integrated, MAX1133BEAP-T Datasheet - Page 7

• Manufacturer Part Number: MAX1133BEAP-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1133BEAP-T

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 200 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended
• Snr: 92 dB
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-20
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

(MAX1132/MAX1133: AV
bipolar input, external REF = +4.096V, 0.22µF bypassing on REFADJ, 2.2µF on REF, 1µF on CREF, T
PIN
10
11
12
1
2
3
4
5
6
7
8
9
REFADJ
SSTRB
NAME
AGND
DGND
SHDN
DOUT
AV
REF
RST
P2
P1
P0
DD
_______________________________________________________________________________________
120
110
100
90
80
70
60
50
40
30
20
10
Reference Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In
internal reference mode, the reference buffer provides a +4.096V nominal output, externally adjustable at
REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to AV
AGND with a 2.2µF capacitor when using the internal reference.
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to AGND with 0.22µF. When using an
external reference, connect REFADJ to AV
Analog Ground. This is the primary analog ground (Star Ground).
Analog Supply. 5V ±5%. Bypass AV
Digital Ground
Shutdown Control Input. Drive SHDN low to put the ADC in shutdown mode.
User-Programmable Output 2
User-Programmable Output 1
User-Programmable Output 0
Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC begins a conversion and goes
high when the conversion is finished. In external clock mode, SSTRB pulses high for one clock period
before the MSB decision. It is high impedance when CS is high in external clock mode.
Serial Data Output. MSB first, straight binary format for unipolar input, two’s complement for bipolar input.
Each bit is clocked out of DOUT at the falling edge of SCLK.
Reset Inp ut. D r i ve RST l ow to p ut the d evi ce i n the p ow er - on d efaul t m od e. S ee the P ow er - O n Reset secti on.
DD
0
16-Bit ADC, 200ksps, 5V Single-Supply
0.1
= DV
DD
= +5V , f
FREQUENCY (kHz)
1
SFDR PLOT
SCLK
f
SAMPLE
Typical Operating Characteristics (continued)
10
= 4.8MHz, external clock (50% duty cycle), 24 clocks/conversion (200ksps),
= 200kHz
100
DD
to AGND (pin 3) with a 0.1µF capacitor.
DD
-100
-110
-30
-40
-10
-20
-50
-60
-70
-80
-90
to disable the internal bandgap reference.
0
FUNCTION
0.1
FREQUENCY (kHz)
1
THD PLOT
with Reference
f
SAMPLE
10
= 200kHz
A
= 25°C, unless otherwise noted.)
100
Pin Description
DD
. Bypass to
7