MAX1282AEEE Maxim Integrated, MAX1282AEEE Datasheet - Page 12
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MAX1282AEEE
Manufacturer Part Number
MAX1282AEEE
Description
Analog to Digital Converters - ADC
Manufacturer
Maxim Integrated
Datasheet
1.MAX1282BCUE.pdf
(23 pages)
Specifications of MAX1282AEEE
Number Of Channels
4/2
Architecture
SAR
Conversion Rate
400 KSPs
Resolution
12 bit
Input Type
Single-Ended/Pseudo-Differential
Interface Type
4-Wire (SPI, Microwire, QSPI, TMS320)
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Power Dissipation
535 mW
Number Of Converters
1
Voltage Reference
2.5 V
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, the difference of
verted. At the end of the conversion, the positive input
connects back to IN+ and C
signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
t
the signal and the minimum time needed for the signal
to be acquired. It is calculated by the following equa-
tion:
where R
the input signal; t
(MAX1282) or 625ns (MAX1283). Note that source
impedances below 2kΩ do not significantly affect the
ADC’s AC performance.
The ADC’s input tracking circuitry has a 6MHz
(MAX1282) or 3MHz (MAX1283) small-signal band-
width, so it is possible to digitize high-speed transient
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
Table 1. Channel Selection in Single-Ended Mode
Table 2. Channel Selection in Pseudo-Differential Mode (SGL/DIF = 0)
12
ACQ
SEL2
SEL2
, is the maximum time the device takes to acquire
______________________________________________________________________________________
0
1
0
1
0
0
1
1
IN
= 800Ω and R
t
ACQ
SEL1
= 9
0
0
1
1
ACQ
SEL1
✕
0
1
0
1
(R
S
is never less than 400ns
S
= the source impedance of
+ R
HOLD
IN
SEL0
[(
Input Bandwidth
)
1
1
0
0
charges to the input
IN+) - (IN-)
✕
18pF
SEL0
1
0
1
0
Track/Hold
]
CH0
is con-
+
CH0
+
–
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate by using under-
sampling techniques. To avoid high-frequency signals
being aliased into the frequency band of interest, anti-
alias filtering is recommended.
Internal protection diodes, which clamp the analog input
to V
from GND - 0.3V to V
However, for accurate conversions near full scale, the
inputs must not exceed V
lower than GND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not allow the input current to exceed 2mA.
Start a conversion by clocking a control byte into DIN.
With CS low, each rising edge on SCLK clocks a bit from
DIN into the MAX1282/MAX1283’s internal shift register.
After CS falls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 3 shows the control-byte format.
The MAX1282/MAX1283 are compatible with SPI/
QSPI/MICROWIRE devices. For SPI, select the correct
clock polarity and sampling edge in the SPI control reg-
isters: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI,
and QSPI all transmit a byte and receive a byte at the
same time. Using the Typical Operating Circuit, the sim-
plest software interface requires only three 8-bit transfers
to perform a conversion (one 8-bit transfer to configure
the ADC, and two more 8-bit transfers to clock out the
CH1
+
DD1
(SGL/DIF = 1)
and GND, allow the channel input pins to swing
CH1
+
–
CH2
+
DD1
Analog Input Protection
DD1
Starting a Conversion
CH2
+ 0.3V without damage.
+
–
by more than 50mV or be
CH3
+
CH3
COM
+
–
–
–
–
–