MAX1203BC/D Maxim Integrated, MAX1203BC/D Datasheet - Page 9

• Manufacturer Part Number: MAX1203BC/D
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1203BC/D

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: 71 dB
• Interface Type: 4-Wire (SPI, Microwire, TMS320)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Power Dissipation: 640 mW
• Number Of Converters: 1
• Voltage Reference: 4.096 V

The MAX1202/MAX1203 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 12-bit digital output. A flexible ser-
ial interface provides easy interface to 3V microproces-
sors (µPs). Figure 3 is the MAX1202/MAX1203 block
diagram.
Figure 4 shows the ADC’s analog comparator’s sam-
pling architecture. In single-ended mode, IN+ is inter-
nally switched to CH0–CH7 and IN- is switched to
GND. In differential mode, IN+ and IN- are selected
from pairs of CH0/CH1, CH2/CH3, CH4/CH5, and
CH6/CH7. Configure the channels using Tables 3
and 4.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential such that only the signal at IN+ is
sampled. The return side (IN-) must remain stable (typi-
cally within ±0.5LSB, within ±0.1LSB for best results)
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
_______________Detailed Description
DOUT
a. High-Z to V
DOUT
3k
3k
OH
GND
a. V
and V
GND
OH
OL
_______________________________________________________________________________________
to High-Z
to V
OH
Pseudo-Differential Input
C
LOAD
C
LOAD
b. High-Z to V
DOUT
5V, 8-Channel, Serial, 12-Bit ADCs
DOUT
b. V
+3.3V
OL
OL
+3.3V
to High-Z
and V
3k
C
GND
LOAD
3k
C
GND
OH
LOAD
to V
OL
with 3V Digital Interface
with respect to GND during a conversion. To do this,
connect a 0.1µF capacitor from IN- (of the selected
analog input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit is entered. The T/H switch opens at the end of
the acquisition interval, retaining charge on C
sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching C
negative input (IN-). In single-ended mode, IN- is sim-
ply GND. This unbalances node ZERO at the compara-
tor’s input. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 12-bit resolution.
This action is equivalent to transferring a charge of
16pF x [(V
weighted capacitive DAC, which in turn forms a digital
representation of the analog input signal.
Figure 3. Block Diagram
REFADJ
SHDN
SCLK
GND
CH3
CH4
CH5
CH6
CH7
CH0
CH1
CH2
DIN
REF
CS
18
19
17
10
13
12
11
1
2
3
4
5
6
7
8
IN
REGISTER
ANALOG
INPUT
SHIFT
INPUT
MUX
+) - (V
REFERENCE
(MAX1202)
HOLD
+2.44V
from the positive input (IN+) to the
MAX1202
MAX1203
IN
CONTROL
T/H
LOGIC
-)] from C
20k
A
+4.096V
IN
CLOCK
1.68
CLOCK
12-BIT
INT
REF
SAR
ADC
HOLD
OUT
REGISTER
OUTPUT
SHIFT
to the binary-
HOLD
HOLD
14
9
15
16
20
DOUT
SSTRB
V
VL
V
DD
SS
. The
as a
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