ispLSI 3448-90LB432 Lattice, ispLSI 3448-90LB432 Datasheet

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ispLSI 3448-90LB432

Manufacturer Part Number
ispLSI 3448-90LB432
Description
CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
Manufacturer
Lattice
Datasheet

Specifications of ispLSI 3448-90LB432

Product Category
CPLD - Complex Programmable Logic Devices
Memory Type
EEPROM
Number Of Macrocells
256
Maximum Operating Frequency
100 MHz
Delay Time
15 ns
Number Of Programmable I/os
224
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Package / Case
BGA
Mounting Style
SMD/SMT
Factory Pack Quantity
21
Supply Current
470 mA
Supply Voltage - Max
5.25 V
Supply Voltage - Min
4.75 V
• HIGH-DENSITY PROGRAMMABLE LOGIC
• HIGH-PERFORMANCE E
• ispLSI FEATURES:
• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE
• OFFERS THE EASE OF USE AND FAST SYSTEM
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
3448_06
Features
— 224 I/O
— 20000 PLD Gates
— 672 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
— Small Logic Block Size for Random Logic
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
— 5V In-System Programmable (ISP™) Using Lattice
— Increased Manufacturing Yields, Reduced Time-to-
— Reprogram Soldered Devices for Faster Debugging
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
— Enhanced Pin Locking Capability
— Five Dedicated Clock Inputs
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to Mini-
— Flexible I/O Placement
— Optimized Global Routing Pool Provides Global
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
— PC and UNIX Platforms
Market, and Improved Product Quality
ISP or Boundary Scan Test (IEEE 1149.1) Protocol
Machines, Address Decoders, etc.
f
t
Logic and Structured Designs
mize Switching Noise
Interconnectivity
Tools, Timing Simulator and ispANALYZER™
max = 90 MHz Maximum Operating Frequency
pd = 12 ns Propagation Delay
2
CMOS
®
TECHNOLOGY
1
In-System Programmable High Density PLD
The ispLSI 3448 is a High-Density Programmable Logic
Device containing 672 Registers, 224 Universal I/Os, five
Dedicated Clock Inputs, 14 Output Routing Pools (ORP)
and a Global Routing Pool (GRP) which allows complete
inter-connectivity between all of these elements. The
ispLSI 3448 features 5V in-system programmability and
in-system diagnostic capabilities. The ispLSI 3448 offers
non-volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 3448 device is the
Twin Generic Logic Block (Twin GLB) labelled A0, A1...N3.
There are a total of 56 of these Twin GLBs in the ispLSI
3448 device. Each Twin GLB has 24 inputs, a program-
mable AND array and two OR/Exclusive-OR Arrays, and
eight outputs which can be configured to be either com-
binatorial or registered. All Twin GLB inputs come from
the GRP.
Functional Block Diagram
Description
Boundary
Scan
K0
K1
K2
K3
N0
N1
N2
N3
Output Routing Pool (ORP)
Output Routing Pool (ORP)
J3
A0
J2
A1
J1
A2
Global Routing Pool
J0
A3
ispLSI
(GRP)
...
...
Output Routing Pool (ORP)
Output Routing Pool (ORP)
H3
C0
Array
Array
OR
OR
C1
H2
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
®
February 2000
C2
H1
3448
Twin
GLB
H0
C3
G3
G2
G1
G0
D3
D2
D1
D0
0139/3448

Related parts for ispLSI 3448-90LB432

ispLSI 3448-90LB432 Summary of contents

Page 1

... The ispLSI 3448 offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 3448 device is the Twin Generic Logic Block (Twin GLB) labelled A0, A1...N3. There are a total these Twin GLBs in the ispLSI 3448 device ...

Page 2

... Functional Block Diagram Figure 1. ispLSI 3448 Functional Block Diagram Input Bus TOE Output Routing Pool I I/O 2 I/O 3 I I/O 6 I/O 7 I I/O 10 I/O 11 I I/O 14 I/O 15 I I/O 18 I/O 19 I I/O 22 I/O 23 I I/O 26 I/O 27 I I/O 30 I/O 31 I I/O 34 I/O 35 I ...

Page 3

... I/O cells. The table below lists key attributes of the device along with the number of resources available. An additional feature of the ispLSI 3448 is the Boundary Scan capability, which is composed of cells connected between the on-chip system logic and the device’s inputs and outputs. All I/O have associated boundary scan registers, with 3-state I/O using three boundary scan registers and inputs using one ...

Page 4

... Supply Voltage CC V Input Low Voltage IL V Input High Voltage IH Capacitance (T =25 C,f=1.0 MHz) A SYMBOL PARAMETER C I/O Capacitance 1 C Clock Capacitance 2 Data Retention Specifications PARAMETER Data Retention ispLSI Erase/Reprogram Cycles Specifications ispLSI 3448 1 +1.0V CC +1.0V CC PARAMETER TYPICAL 10 11 MINIMUM 20 10000 4 MIN. MAX. UNITS 4.75 5. ...

Page 5

... Refer to the Power Consumption CC section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum Specifications ispLSI 3448 Figure 2. Test Load GND to 3. 10% to 90% 1.5V 1.5V Device ...

Page 6

... Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. 5. Reference Switching Test Conditions section. Specifications ispLSI 3448 Over Recommended Operating Conditions 1 ...

Page 7

... ORP Bypass Delay orpbp 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Specifications ispLSI 3448 1 DESCRIPTION 3 7 -90 -70 UNITS MIN ...

Page 8

... Global OE Pad Buffer goe t toe 55 Test OE Pad Buffer 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. Specifications ispLSI 3448 1 Over Recommended Operating Conditions DESCRIPTION 8 -90 -70 UNITS MIN. MAX. ...

Page 9

... Clock (max) + Reg co + Output iobp + grp + ptck(max (#24 + #30 + #44) + (#40) + (#45 + #47) = (2.3 + 3.2 + 3.7) + (0.5) + (1.5 + 2.5) 13.7 ns Note: Calculations are based on timing specs for the ispLSI 3448-90L. Specifications ispLSI 3448 GLB Feedback #31 # Bypass GLB Reg Bypass #33 # GLB Reg XOR Delays Delay ...

Page 10

... Figure 3. Typical Device Power Consumption vs fmax 1000 I CC can be estimated for the ispLSI 3448 using the following equation PTs * 0.46 nets * Max. freq * 0.01) where PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max ...

Page 11

... AH9, AH10, AH11, AH12, AH13, AH14, AH15, AH16, AH17, AH18, AH19, AH20, AH21, AH22, AH23, AH24, AH25, AH26, AH27, AH28, AJ3, AJ7, AJ11, AJ14, AJ18, AJ21, AJ25, AJ29, AK2, AK30 1. NCs are not to be connected to any active signals, VCC or GND. Specifications ispLSI 3448 Description 432-Ball BGA ...

Page 12

... AK10 I/O 31 AL27 I/O 69 AJ10 I/O 32 AJ26 I/O 70 AL9 I/O 33 AK26 I/O 71 AJ9 I/O 34 AL26 I/O 72 AL8 I/O 35 AK25 I/O 73 AK8 I/O 36 AL25 I/O 74 AJ8 I/O 37 AJ24 I/O 75 AL7 Specifications ispLSI 3448 Signal BGA Signal BGA I/O 114 R1 I/O 76 AK7 I/O 115 P1 I/O 77 AL6 I/O 116 N1 I/O 78 AK6 I/O 117 N3 I/O 79 AJ6 I/O 118 M1 I/O 80 AL5 I/O 119 M2 I/O 81 AL4 I/O 120 ...

Page 13

... Signal Configuration ispLSI 3448 432-Ball BGA Signal Diagram I/O I/O I/O I/O I/O I/O A GND GND VCC 192 191 188 186 183 181 I/O I/O I/O I/O I GND NC GND GND 195 194 189 187 184 I/O I/O I/O I/O I/O I VCC NC NC 198 ...

Page 14

... MHz max Ordering Information FAMILY fmax (MHz) tpd (ns ispLSI 70 15 Specifications ispLSI 3448 – XXXX X Grade COMMERCIAL ORDERING NUMBER ispLSI 3448-90LB432 ispLSI 3448-70LB432 14 Blank = Commercial Package B432 = BGA Power L = Low 0212/3448 PACKAGE 432-Ball BGA 432-Ball BGA Table 2-0041/3448 ...

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