MAX1137EUA-T Maxim Integrated, MAX1137EUA-T Datasheet - Page 12

• Manufacturer Part Number: MAX1137EUA-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1137EUA-T

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 94.4 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: Yes
• Interface Type: I2C
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: uMAX
• Maximum Power Dissipation: 362 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal 4.096 V

A bus master initiates communication with a slave device
by issuing a START condition followed by a slave
address. When idle, the MAX1136–MAX1139 continuous-
ly wait for a START condition followed by their slave
address. When the MAX1136–MAX1139 recognize their
slave address, they are ready to accept or send data.
The slave address has been factory programmed and is
always 0110100 for the MAX1136/MAX1137, and
0110101 for MAX1138/MAX1139 (Figure 7). The least sig-
nificant bit (LSB) of the address byte (R/W) determines
whether the master is writing to or reading from the
MAX1136–MAX1139 (R/W = 0 selects a write condition,
R/W = 1 selects a read condition). After receiving the
address, the MAX1136–MAX1139 (slave) issues an
acknowledge by pulling SDA low for one clock cycle.
At power-up, the MAX1136–MAX1139 bus timing is set
for fast mode (F/S-mode) which allows conversion rates
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
Figure 7. MAX1136/MAX1137 Slave Address Byte
Figure 8. F/S-Mode to HS-Mode Transfer
12
______________________________________________________________________________________
SDA
SCL
S
SDA
SCL
MAX1136/MAX1137
MAX1138/MAX1139
0
S
DEVICE
0
0
MAX1136/MAX1137
1
1
0
2
SLAVE ADDRESS
0110100
0110101
HS-MODE MASTER CODE
Slave Address
1
0
Bus Timing
3
SLAVE ADDRESS
F/S-MODE
0
1
4
1
X
5
up to 22.2ksps. The MAX1136–MAX1139 must operate
in high-speed mode (HS-mode) to achieve conversion
rates up to 94.4ksps. Figure 1 shows the bus timing for
the MAX1136–MAX1139’s 2-wire interface.
At power-up, the MAX1136–MAX1139 bus timing is set
for F/S-mode. The bus master selects HS-mode by
addressing all devices on the bus with the HS-mode
master code 0000 1XXX (X = don’t care). After success-
fully receiving the HS-mode master code, the
MAX1136–MAX1139 issue a not-acknowledge allowing
SDA to be pulled high for one clock cycle (Figure 8).
After the not-acknowledge, the MAX1136–MAX1139 are
in HS-mode. The bus master must then send a repeated
START followed by a slave address to initiate HS-mode
communication. If the master generates a STOP condi-
tion the MAX1136–MAX1139 returns to F/S-mode.
0
X
6
0
X
7
R/W
A
8
A
9
Sr
HS-MODE
HS-Mode